srctrl.in

free hardware ip core about sparcv8,a soc cpu in vhdl

  mainmenu_option next_comment
  comment '8/32-bit PROM/SRAM controller '
    bool 'Enable 8/32-bit PROM/SRAM controller    ' CONFIG_SRCTRL
    if [ "$CONFIG_SRCTRL" = "y" ]; then
      bool '8-bit PROM interface ' CONFIG_SRCTRL_8BIT
      int 'PROM waitstates' CONFIG_SRCTRL_PROMWS 3
      int 'RAM waitstates' CONFIG_SRCTRL_RAMWS 0
      int 'IO waitstates' CONFIG_SRCTRL_IOWS 0
      bool 'Use read-modify-write for sub-word writes  ' CONFIG_SRCTRL_RMW
      choice 'SRAM banks' \
   	  "1		CONFIG_SRCTRL_SRBANKS1 \
   	   2		CONFIG_SRCTRL_SRBANKS2 \
   	   3		CONFIG_SRCTRL_SRBANKS3 \
   	   4		CONFIG_SRCTRL_SRBANKS4 \
   	   5		CONFIG_SRCTRL_SRBANKS5" 1

      choice 'SRAM bank size (kb) (0 for programmable)' \
   	  "8		   CONFIG_SRCTRL_BANKSZ0 \
   	   16		   CONFIG_SRCTRL_BANKSZ1 \
   	   32		   CONFIG_SRCTRL_BANKSZ2 \
   	   64		   CONFIG_SRCTRL_BANKSZ3 \
   	   128		CONFIG_SRCTRL_BANKSZ4 \
   	   256		CONFIG_SRCTRL_BANKSZ5 \
   	   512		CONFIG_SRCTRL_BANKSZ6 \
   	   1024		CONFIG_SRCTRL_BANKSZ7 \
   	   2048		CONFIG_SRCTRL_BANKSZ8 \
   	   4096		CONFIG_SRCTRL_BANKSZ9 \
   	  	8192	   CONFIG_SRCTRL_BANKSZ10 \
   	  	16384	   CONFIG_SRCTRL_BANKSZ11 \
   	   32768		CONFIG_SRCTRL_BANKSZ12 \
   	   65536  	CONFIG_SRCTRL_BANKSZ13" 0
      int 'PROM bank select address bit (0 - 28)' CONFIG_SRCTRL_ROMASEL 19
    fi
  endmenu