srctrl.in.help

free hardware ip core about sparcv8,a soc cpu in vhdl

PROM/SRAM memory controller
CONFIG_SRCTRL
  Say Y here to enable a simple (and small) PROM/SRAM memory controller.
  The controller has a fixed number of waitstates, and is primarily
  intended for FPGA implementations. The RAM data bus is always 32 bits,
  the PROM can be configured to either 8 or 32 bits (hardwired).

8-bit memory support
CONFIG_SRCTRL_8BIT
  If you say Y here, the simple PROM/SRAM memory controller will
  implement 8-bit PROM mode.

PROM waitstates
CONFIG_SRCTRL_PROMWS
  Select the number of waitstates for PROM access.

RAM waitstates
CONFIG_SRCTRL_RAMWS
  Select the number of waitstates for RAM access.

IO waitstates
CONFIG_SRCTRL_IOWS
  Select the number of waitstates for IO access.

Read-modify-write support
CONFIG_SRCTRL_RMW
  Say Y here to perform byte- and half-word writes as a
  read-modify-write sequence. This is necessary if your
  SRAM does not have individual byte enables. If you are
  unsure, it is safe to say Y.

SRAM bank select
CONFIG_SRCTRL_SRBANKS
  Select number of SRAM banks.

SRAM bank size select
CONFIG_SRCTRL_BANKSZ
  Select size of SRAM banks in kBytes.

PROM address bit select
CONFIG_SRCTRL_ROMASEL
  Select address bit for PROM bank decoding.