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📄 greth.vhd

📁 free hardware ip core about sparcv8,a soc cpu in vhdl
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    txlength        : std_logic_vector(10 downto 0);    txburstcnt      : std_logic_vector(burstbits downto 0);    tfwpnt          : std_logic_vector(txfabits-1 downto 0);    tfrpnt          : std_logic_vector(txfabits-1 downto 0);    tfcnt           : std_logic_vector(txfabits downto 0);     txcnt           : std_logic_vector(10 downto 0);    txstart         : std_ulogic;    txirqgen        : std_ulogic;    txstatus        : std_logic_vector(1 downto 0);    txvalid         : std_ulogic;     txdata          : std_logic_vector(31 downto 0);    txprevaddr      : std_logic_vector(31 downto 0);    writeok         : std_ulogic;    txread          : std_logic_vector(nsync-1 downto 0);    txrestart       : std_logic_vector(nsync downto 0);    txdone          : std_logic_vector(nsync downto 0);    txstart_sync    : std_ulogic;    txreadack       : std_ulogic;    txdataav        : std_ulogic;              --master rx interface     rxdsel          : std_logic_vector(9 downto 3);    rmsto           : eth_rx_ahb_in_type;    rxdstate        : rxd_state_type;    rxstatus        : std_logic_vector(3 downto 0);    rxaddr          : std_logic_vector(31 downto 2);    rxlength        : std_logic_vector(10 downto 0);    rxbytecount     : std_logic_vector(10 downto 0);    rxwrap          : std_ulogic;    rxirq           : std_ulogic;    rfwpnt          : std_logic_vector(fabits-1 downto 0);    rfrpnt          : std_logic_vector(fabits-1 downto 0);    rfcnt           : std_logic_vector(fabits downto 0);    rxcnt           : std_logic_vector(10 downto 0);    rxdoneold       : std_ulogic;    rxdoneack       : std_ulogic;     rxdone          : std_logic_vector(nsync-1 downto 0);    rxstart         : std_logic_vector(nsync downto 0);    rxwrite         : std_logic_vector(nsync-1 downto 0);    rxwriteack      : std_ulogic;     rxburstcnt      : std_logic_vector(burstbits downto 0);    addrnok         : std_ulogic;    ctrlpkt         : std_ulogic;    check           : std_ulogic;    checkdata       : std_logic_vector(31 downto 0);    usesizefield    : std_ulogic;    rxden           : std_ulogic;    gotframe        : std_ulogic;    bcast           : std_ulogic;         --mdio    mdccnt          : std_logic_vector(7 downto 0);    mdioclk         : std_ulogic;    mdioclkold      : std_ulogic;    mdio_state      : mdio_state_type;    mdioo           : std_ulogic;    mdioi           : std_ulogic;    mdioen          : std_ulogic;    cnt             : std_logic_vector(4 downto 0);    error           : std_ulogic;    done            : std_ulogic;    start           : std_ulogic;    --edcl    edclrstate      : edclrstate_type;    duplexstate     : duplexstate_type;    edclactive      : std_ulogic;    nak             : std_ulogic;    ewr             : std_ulogic;    write           : std_logic_vector(wsz-1 downto 0);    seq             : std_logic_vector(13 downto 0);    abufs           : std_logic_vector(bselbits downto 0);    tpnt            : std_logic_vector(bselbits-1 downto 0);    rpnt            : std_logic_vector(bselbits-1 downto 0);    tcnt            : std_logic_vector(bpbits-1 downto 0);    rcntm           : std_logic_vector(bpbits-1 downto 0);    rcntl           : std_logic_vector(bpbits-1 downto 0);    ipcrc           : std_logic_vector(17 downto 0);    applength       : std_logic_vector(15 downto 0);    oplen           : std_logic_vector(9 downto 0);    udpsrc          : std_logic_vector(15 downto 0);    ecnt            : std_logic_vector(3 downto 0);    tarp            : std_ulogic;    tnak            : std_ulogic;    tedcl           : std_ulogic;    tedclstarted    : std_ulogic;    edclbcast       : std_ulogic;  end record;  --transmitter types  type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,    fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,    check_attempts);  type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);  type tx_reg_type is record    --deference process    def_state        : def_state_type;     ifg_cycls        : std_logic_vector(ifg_bits-1 downto 0);    deferring        : std_ulogic;     was_transmitting : std_ulogic;        --tx process    main_state   : tx_state_type;    transmitting : std_ulogic;    tx_en        : std_ulogic;    txd          : std_logic_vector(3 downto 0);    cnt          : std_logic_vector(3 downto 0);    icnt         : std_logic_vector(1 downto 0);    crc          : std_logic_vector(31 downto 0);    crc_en       : std_ulogic;     byte_count   : std_logic_vector(10 downto 0);    slot_count   : std_logic_vector(6 downto 0);    random       : std_logic_vector(9 downto 0);    delay_val    : std_logic_vector(9 downto 0);    retry_cnt    : std_logic_vector(4 downto 0);    status       : std_logic_vector(1 downto 0);     data         : std_logic_vector(31 downto 0);        --synchronization    read         : std_ulogic;    done         : std_ulogic;    restart      : std_ulogic;    start        : std_logic_vector(nsync downto 0);    read_ack     : std_logic_vector(nsync-1 downto 0);    crs          : std_logic_vector(1 downto 0);    col          : std_logic_vector(1 downto 0);    fullduplex   : std_logic_vector(1 downto 0);        --rmii    crs_act      : std_ulogic;    crs_prev     : std_ulogic;    speed        : std_logic_vector(1 downto 0);    rcnt         : std_logic_vector(3 downto 0);    switch       : std_ulogic;    txd_msb      : std_logic_vector(1 downto 0);    zero         : std_ulogic;    rmii_crc_en  : std_ulogic;  end record;  --receiver types  type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,                         wait_report, check_crc, discard_packet);    type rx_reg_type is record    er              : std_ulogic;    en              : std_ulogic;    rxd             : std_logic_vector(3 downto 0);                     crc             : std_logic_vector(31 downto 0);    sync_start      : std_ulogic;    gotframe        : std_ulogic;    start           : std_ulogic;    write           : std_ulogic;     done            : std_ulogic;     odd_nibble      : std_ulogic;    byte_count      : std_logic_vector(10 downto 0);    data            : std_logic_vector(31 downto 0);    dataout         : std_logic_vector(31 downto 0);    rx_state        : rx_state_type;    status          : std_logic_vector(3 downto 0);    write_ack       : std_logic_vector(nsync-1 downto 0);    done_ack        : std_logic_vector(nsync downto 0);    rxen            : std_logic_vector(1 downto 0);    --rmii    enold           : std_ulogic;    act             : std_ulogic;    dv              : std_ulogic;    cnt             : std_logic_vector(3 downto 0);    rxd2            : std_logic_vector(1 downto 0);    speed           : std_logic_vector(1 downto 0);    zero            : std_ulogic;  end record;  --host signals  signal irst             : std_ulogic;  signal rxenable         : std_ulogic;  signal vcc              : std_ulogic;    signal rxfi             : fifo_access_in_type;  signal txfi             : tx_fifo_access_in_type;   signal rxfo             : fifo_access_out_type;  signal txfo             : tx_fifo_access_out_type;  signal eri              : edcl_ram_in_type;  signal ero              : edcl_ram_out_type;  signal tmsto            : eth_tx_ahb_in_type;  signal tmsti            : eth_tx_ahb_out_type;  signal rmsto            : eth_rx_ahb_in_type;  signal rmsti            : eth_rx_ahb_out_type;  --DEBUG!!!!!--   signal dv_d               : std_ulogic;--   signal rdv_d              : std_ulogic;--   signal rxd_d              : std_logic_vector(3 downto 0);--   signal act_d              : std_ulogic;  signal r, rin           : reg_type;  --transmitter signals  signal tr, trin         : tx_reg_type;  signal txclk            : std_ulogic;  signal txrst            : std_ulogic;    --receiver signals  signal rr, rrin         : rx_reg_type;  signal rxclk            : std_ulogic;  signal rxrst            : std_ulogic;    attribute keep of rxclk : signal is true;  attribute syn_keep of rxclk : signal is true;  attribute syn_preserve of rxclk : signal is true;begin    --debug--   etho.tarp       <= r.tarp;--   etho.txrestart  <= r.txrestart(0);--   etho.txstart    <= r.txstart_sync;--   etho.txdone     <= r.txdone(0);--   etho.rxstart    <= rr.start;--   etho.rxgotframe <= r.gotframe;--   etho.rxdone     <= r.rxdoneold;--   etho.edclact    <= r.edclactive;--   etho.dv         <= dv_d;--   etho.rdv        <= rdv_d;--   etho.rxd_d      <= rxd_d;--   etho.act        <= act_d;--   etho.seq        <= r.seq;--  etho.abufs      <= r.abufs;--   etho.tfcnt      <= r.tfcnt;--   etho.rfcnt      <= r.rfcnt;--  etho.tpnt       <= r.tpnt;  --  etho.rpnt       <= r.rpnt;  --   debug : process(r, rr, tr) is--   begin--     case tr.main_state is--       when idle =>--         etho.trmain <= "0000";--       when preamble =>--         etho.trmain <= "0001";--       when sfd =>--         etho.trmain <= "0010";--       when data1 =>--         etho.trmain <= "0011";--       when data2 =>--         etho.trmain <= "0100";--       when pad1 =>--         etho.trmain <= "0101";--       when pad2 =>--         etho.trmain <= "0110";--       when fcs =>--         etho.trmain <= "0111";--       when finish =>--         etho.trmain <= "1000";--       when calc_backoff =>--         etho.trmain <= "1001";--       when wait_backoff =>--         etho.trmain <= "1010";--       when send_jam =>--         etho.trmain <= "1011";--       when send_jam2 =>--         etho.trmain <= "1100";--       when check_attempts =>--         etho.trmain <= "1101";--       when others =>--         etho.trmain <= "1110";--     end case;    --     case tr.def_state is--       when monitor =>--         etho.trdef <= "000";--       when def_on =>--         etho.trdef <= "001";--       when ifg1 =>--         etho.trdef <= "010";--       when ifg2 =>--         etho.trdef <= "011";--       when frame_waitingst =>--         etho.trdef <= "100";--       when others =>--         etho.trdef <= "101";--     end case;--     case rr.rx_state is--       when idle =>--         etho.rrmain <= "0000";--       when wait_sfd =>--         etho.rrmain <= "0001";--       when data1 =>--         etho.rrmain <= "0010";--       when data2 =>--         etho.rrmain <= "0011";--       when errorst =>--         etho.rrmain <= "0100";--       when report_status =>--         etho.rrmain <= "0101";--       when wait_report =>--         etho.rrmain <= "0110";--       when check_crc =>--         etho.rrmain <= "0111";--       when discard_packet =>--         etho.rrmain <= "1000";--       when others =>--         etho.rrmain <= "1001";--     end case;--     case r.txdstate is--       when idle =>--         etho.txdma <= "0000";--       when read_desc =>--         etho.txdma <= "0001";--       when check_desc =>--         etho.txdma <= "0010";--       when req =>--         etho.txdma <= "0011";--       when fill_fifo =>--         etho.txdma <= "0100";--       when check_result =>--         etho.txdma <= "0101";--       when write_result =>--         etho.txdma <= "0110";--       when readhdr =>--         etho.txdma <= "0111";--       when start =>--         etho.txdma <= "1000";--       when wrbus =>--         etho.txdma <= "1001";--       when etdone =>--         etho.txdma <= "1010";--       when getlen =>--         etho.txdma <= "1011";--       when others =>--         etho.txdma <= "1100";--     end case;--     case r.rxdstate is--       when idle =>--         etho.rxdma <= "0000";--       when read_desc =>--         etho.rxdma <= "0001";--       when check_desc =>--         etho.rxdma <= "0010";--       when read_req =>--         etho.rxdma <= "0011";--       when read_fifo =>--         etho.rxdma <= "0100";--       when discard =>--         etho.rxdma <= "0101";--       when write_status =>--         etho.rxdma <= "0110";--       when write_status2 =>--         etho.rxdma <= "0111";--       when others =>--         etho.rxdma <= "1000";--     end case;--     case r.edclrstate is--       when idle =>--         etho.tedcl <= "0000";--       when wrda =>--         etho.tedcl <= "0001";--       when wrdsa =>

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