can_mc.in.help

free hardware ip core about sparcv8,a soc cpu in vhdl

CAN interface enable
CONFIG_CAN_ENABLE
  Say Y here to enable one or more CAN cores. The cores has one
  AHB slave interface for accessing the control registers. The CAN core
  is register-compatible with the SAJ1000 core from Philips, with a
  few exceptions. See the GRLIP IP manual for details.

CONFIG_CAN_NUM
  Number of CAN cores. The module allows up to 8 independent
  CAN cores to be implemented.

CAN register address
CONFIG_CANIO
  The control registers of each CAN core occupies 256 bytes, and 
  address space needed for the full module is thus 2 Kbyte. The cores
  are mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). 
  This setting defines at which address in the I/O area the registers
  appear (HADDR[19:8]).

CAN interrupt
CONFIG_CANIRQ
  Defines which interrupt number the CAN core will generate.

CAN interrupt
CONFIG_CANSEPIRQ
  Say Y here to assign an individual interrupt to each CAN core,
  starting from the base interrupt number. If set to N, all
  CAN cores will generate the same interrupt.

CAN FT memories
CONFIG_CAN_FT
  If you say Y here, the CAN FIFOs will be implemented using
  SEU protected RAM blocks. Only applicable to the FT version
  of grlib.

CAN Synchronous reset
CONFIG_CAN_SYNCRST
  If you say Y here, the CAN core will be implemented with
  synchronous reset rather than asynchronous. This is needed
  when the target library does not implement registers with
  async reset. Unless you know what you are doing, say N.