clkgen_ut25.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity: 	clkgen_ut025crh
-- File:	clkgen_ut025crh.vhd
-- Author:	Jiri Gaisler Gaisler Research
-- Description:	Clock generator for Aeroflex UT25
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ut025crh;
use ut025crh.clkgate;
-- pragma translate_on

entity clkand_ut025crh is
  port(
    i      :  in  std_ulogic;
    en     :  in  std_ulogic;
    o      :  out std_ulogic
  );
end entity;

architecture rtl of clkand_ut025crh is

component clkgate 
  port(
    A : in STD_ULOGIC;
    EN: in STD_ULOGIC;
    Y : out STD_ULOGIC
    );
end component;
  
begin
    buf : clkgate port map(A => i, EN => en, Y => o);
end architecture;