leaves.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

end DBLC_3;

-- The DBLC-tree: Level 4

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_128 is
port
(
	PIN: in std_logic_vector(0 to 112);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 96);
	GOUT: out std_logic_vector(0 to 128)
);
end DBLC_4_128;

architecture DBLC_4 of DBLC_4_128 is

begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
	U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 128 generate
	U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;

-- The DBLC-tree: Level 5

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_128 is
port
(
	PIN: in std_logic_vector(0 to 96);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 64);
	GOUT: out std_logic_vector(0 to 128)
);
end DBLC_5_128;

architecture DBLC_5 of DBLC_5_128 is

begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
	U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 128 generate
	U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;

-- The DBLC-tree: Level 6

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_6_128 is
port
(
	PIN: in std_logic_vector(0 to 64);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 0);
	GOUT: out std_logic_vector(0 to 128)
);
end DBLC_6_128;

architecture DBLC_6 of DBLC_6_128 is

begin -- Architecture DBLC_6
	GOUT(0 to 63) <= GIN(0 to 63);
U2: for I in 64 to 127 generate
	U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 128 to 128 generate
	U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I));
end generate U3;
end DBLC_6;

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_128 is
port
(
	A: in std_logic_vector(0 to 127);
	B: in std_logic_vector(0 to 127);
	PBIT, PHI: in std_logic;
	CARRY: in std_logic_vector(0 to 128);
	SUM: out std_logic_vector(0 to 127);
	COUT: out std_logic
);
end XORSTAGE_128;
architecture XORSTAGE of XORSTAGE_128 is

begin -- XORSTAGE
U2:for I in 0 to 63 generate
	U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 64 to 127 generate
	U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT);
end XORSTAGE;

-- The DBLC-tree: All levels encapsulated

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCTREE_128 is
port
(
	PIN:in std_logic_vector(0 to 127);
	GIN:in std_logic_vector(0 to 128);
	PHI:in std_logic;
	GOUT:out std_logic_vector(0 to 128);
	POUT:out std_logic_vector(0 to 0)
);
end DBLCTREE_128;

architecture DBLCTREE of DBLCTREE_128 is

signal INTPROP_0: std_logic_vector(0 to 126);
signal INTGEN_0: std_logic_vector(0 to 128);
signal INTPROP_1: std_logic_vector(0 to 124);
signal INTGEN_1: std_logic_vector(0 to 128);
signal INTPROP_2: std_logic_vector(0 to 120);
signal INTGEN_2: std_logic_vector(0 to 128);
signal INTPROP_3: std_logic_vector(0 to 112);
signal INTGEN_3: std_logic_vector(0 to 128);
signal INTPROP_4: std_logic_vector(0 to 96);
signal INTGEN_4: std_logic_vector(0 to 128);
signal INTPROP_5: std_logic_vector(0 to 64);
signal INTGEN_5: std_logic_vector(0 to 128);
begin -- Architecture DBLCTREE
U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5);
U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLCADDER_128_128 is
port
(
	OPA:in std_logic_vector(0 to 127);
	OPB:in std_logic_vector(0 to 127);
	CIN:in std_logic;
	PHI:in std_logic;
	SUM:out std_logic_vector(0 to 127);
	COUT:out std_logic
);
end DBLCADDER_128_128;
architecture DBLCADDER of DBLCADDER_128_128 is

signal INTPROP: std_logic_vector(0 to 127);
signal INTGEN: std_logic_vector(0 to 128);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 128);

begin -- Architecture DBLCADDER

U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT);
end DBLCADDER;




--
-- Modified Booth algorithm architecture
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity BOOTHCODER_18_18 is
port
(
		OPA: in std_logic_vector(0 to 17);
		OPB: in std_logic_vector(0 to 17);
		SUMMAND: out std_logic_vector(0 to 188)
);
end BOOTHCODER_18_18;
------------------------------------------------------------
-- END: Entities used within the Modified Booth Recoding
------------------------------------------------------------
architecture BOOTHCODER of BOOTHCODER_18_18 is

-- Components used in the architecture

-- Internal signal in Booth structure

signal INV_MULTIPLICAND: std_logic_vector(0 to 17);
signal INT_MULTIPLIER: std_logic_vector(0 to 35);
signal LOGIC_ONE, LOGIC_ZERO: std_logic;
begin
LOGIC_ONE <= '1';
LOGIC_ZERO <= '0';
-- Begin decoder block 1
DEC_0:DECODER -- Decoder of multiplier operand
	port map
	(
		INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3)
	);
-- End decoder block 1
-- Begin partial product 1
INV_MULTIPLICAND(0) <= NOT OPA(0);
PPL_0:PP_LOW
	port map
	(
		INA => OPA(0),INB => INV_MULTIPLICAND(0),
		TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(0)
	);
RGATE_0:R_GATE
	port map
	(
		INA => LOGIC_ZERO,INB => OPB(0),INC => OPB(1),
		PPBIT => SUMMAND(1)
	);
INV_MULTIPLICAND(1) <= NOT OPA(1);
PPM_0:PP_MIDDLE
	port map
	(
		INA => OPA(0),INB => INV_MULTIPLICAND(0),
		INC => OPA(1),IND => INV_MULTIPLICAND(1),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(2)
	);
INV_MULTIPLICAND(2) <= NOT OPA(2);
PPM_1:PP_MIDDLE
	port map
	(
		INA => OPA(1),INB => INV_MULTIPLICAND(1),
		INC => OPA(2),IND => INV_MULTIPLICAND(2),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(3)
	);
INV_MULTIPLICAND(3) <= NOT OPA(3);
PPM_2:PP_MIDDLE
	port map
	(
		INA => OPA(2),INB => INV_MULTIPLICAND(2),
		INC => OPA(3),IND => INV_MULTIPLICAND(3),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(6)
	);
INV_MULTIPLICAND(4) <= NOT OPA(4);
PPM_3:PP_MIDDLE
	port map
	(
		INA => OPA(3),INB => INV_MULTIPLICAND(3),
		INC => OPA(4),IND => INV_MULTIPLICAND(4),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(8)
	);
INV_MULTIPLICAND(5) <= NOT OPA(5);
PPM_4:PP_MIDDLE
	port map
	(
		INA => OPA(4),INB => INV_MULTIPLICAND(4),
		INC => OPA(5),IND => INV_MULTIPLICAND(5),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(12)
	);
INV_MULTIPLICAND(6) <= NOT OPA(6);
PPM_5:PP_MIDDLE
	port map
	(
		INA => OPA(5),INB => INV_MULTIPLICAND(5),
		INC => OPA(6),IND => INV_MULTIPLICAND(6),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(15)
	);
INV_MULTIPLICAND(7) <= NOT OPA(7);
PPM_6:PP_MIDDLE
	port map
	(
		INA => OPA(6),INB => INV_MULTIPLICAND(6),
		INC => OPA(7),IND => INV_MULTIPLICAND(7),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(20)
	);
INV_MULTIPLICAND(8) <= NOT OPA(8);
PPM_7:PP_MIDDLE
	port map
	(
		INA => OPA(7),INB => INV_MULTIPLICAND(7),
		INC => OPA(8),IND => INV_MULTIPLICAND(8),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(24)
	);
INV_MULTIPLICAND(9) <= NOT OPA(9);
PPM_8:PP_MIDDLE
	port map
	(
		INA => OPA(8),INB => INV_MULTIPLICAND(8),
		INC => OPA(9),IND => INV_MULTIPLICAND(9),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(30)
	);
INV_MULTIPLICAND(10) <= NOT OPA(10);
PPM_9:PP_MIDDLE
	port map
	(
		INA => OPA(9),INB => INV_MULTIPLICAND(9),
		INC => OPA(10),IND => INV_MULTIPLICAND(10),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(35)
	);
INV_MULTIPLICAND(11) <= NOT OPA(11);
PPM_10:PP_MIDDLE
	port map
	(
		INA => OPA(10),INB => INV_MULTIPLICAND(10),
		INC => OPA(11),IND => INV_MULTIPLICAND(11),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(42)
	);
INV_MULTIPLICAND(12) <= NOT OPA(12);
PPM_11:PP_MIDDLE
	port map
	(
		INA => OPA(11),INB => INV_MULTIPLICAND(11),
		INC => OPA(12),IND => INV_MULTIPLICAND(12),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(48)
	);
INV_MULTIPLICAND(13) <= NOT OPA(13);
PPM_12:PP_MIDDLE
	port map
	(
		INA => OPA(12),INB => INV_MULTIPLICAND(12),
		INC => OPA(13),IND => INV_MULTIPLICAND(13),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(56)
	);
INV_MULTIPLICAND(14) <= NOT OPA(14);
PPM_13:PP_MIDDLE
	port map
	(
		INA => OPA(13),INB => INV_MULTIPLICAND(13),
		INC => OPA(14),IND => INV_MULTIPLICAND(14),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(63)
	);
INV_MULTIPLICAND(15) <= NOT OPA(15);
PPM_14:PP_MIDDLE
	port map
	(
		INA => OPA(14),INB => INV_MULTIPLICAND(14),
		INC => OPA(15),IND => INV_MULTIPLICAND(15),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(72)
	);
INV_MULTIPLICAND(16) <= NOT OPA(16);
PPM_15:PP_MIDDLE
	port map
	(
		INA => OPA(15),INB => INV_MULTIPLICAND(15),
		INC => OPA(16),IND => INV_MULTIPLICAND(16),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(80)
	);
INV_MULTIPLICAND(17) <= NOT OPA(17);
PPM_16:PP_MIDDLE
	port map
	(
		INA => OPA(16),INB => INV_MULTIPLICAND(16),
		INC => OPA(17),IND => INV_MULTIPLICAND(17),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(90)
	);
PPH_0:PP_HIGH
	port map
	(
		INA => OPA(17),INB => INV_MULTIPLICAND(17),
		TWOPOS => INT_MULTIPLIER(0),TWONEG => INT_MULTIPLIER(1),ONEPOS => INT_MULTIPLIER(2),ONENEG => INT_MULTIPLIER(3),
		PPBIT => SUMMAND(99)
	);
SUMMAND(100) <= '1';
-- Begin partial product 1
-- Begin decoder block 2
DEC_1:DECODER -- Decoder of multiplier operand
	port map
	(
		INA => OPB(1),INB => OPB(2),INC => OPB(3),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7)
	);
-- End decoder block 2
-- Begin partial product 2
PPL_1:PP_LOW
	port map
	(
		INA => OPA(0),INB => INV_MULTIPLICAND(0),
		TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(4)
	);
RGATE_1:R_GATE
	port map
	(
		INA => OPB(1),INB => OPB(2),INC => OPB(3),
		PPBIT => SUMMAND(5)
	);
PPM_17:PP_MIDDLE
	port map
	(
		INA => OPA(0),INB => INV_MULTIPLICAND(0),
		INC => OPA(1),IND => INV_MULTIPLICAND(1),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(7)
	);
PPM_18:PP_MIDDLE
	port map
	(
		INA => OPA(1),INB => INV_MULTIPLICAND(1),
		INC => OPA(2),IND => INV_MULTIPLICAND(2),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(9)
	);
PPM_19:PP_MIDDLE
	port map
	(
		INA => OPA(2),INB => INV_MULTIPLICAND(2),
		INC => OPA(3),IND => INV_MULTIPLICAND(3),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(13)
	);
PPM_20:PP_MIDDLE
	port map
	(
		INA => OPA(3),INB => INV_MULTIPLICAND(3),
		INC => OPA(4),IND => INV_MULTIPLICAND(4),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(16)
	);
PPM_21:PP_MIDDLE
	port map
	(
		INA => OPA(4),INB => INV_MULTIPLICAND(4),
		INC => OPA(5),IND => INV_MULTIPLICAND(5),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(21)
	);
PPM_22:PP_MIDDLE
	port map
	(
		INA => OPA(5),INB => INV_MULTIPLICAND(5),
		INC => OPA(6),IND => INV_MULTIPLICAND(6),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(25)
	);
PPM_23:PP_MIDDLE
	port map
	(
		INA => OPA(6),INB => INV_MULTIPLICAND(6),
		INC => OPA(7),IND => INV_MULTIPLICAND(7),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(31)
	);
PPM_24:PP_MIDDLE
	port map
	(
		INA => OPA(7),INB => INV_MULTIPLICAND(7),
		INC => OPA(8),IND => INV_MULTIPLICAND(8),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(36)
	);
PPM_25:PP_MIDDLE
	port map
	(
		INA => OPA(8),INB => INV_MULTIPLICAND(8),
		INC => OPA(9),IND => INV_MULTIPLICAND(9),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(43)
	);
PPM_26:PP_MIDDLE
	port map
	(
		INA => OPA(9),INB => INV_MULTIPLICAND(9),
		INC => OPA(10),IND => INV_MULTIPLICAND(10),
		TWOPOS => INT_MULTIPLIER(4),TWONEG => INT_MULTIPLIER(5),ONEPOS => INT_MULTIPLIER(6),ONENEG => INT_MULTIPLIER(7),
		PPBIT => SUMMAND(49)
	);