leaves.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

end component;
component WALLACE_34_34
port
(
	SUMMAND: in std_logic_vector(0 to 628);
	CARRY: out std_logic_vector(0 to 65);
	SUM: out std_logic_vector(0 to 66)
);
end component;
component DBLCADDER_128_128
port
(
	OPA:in std_logic_vector(0 to 127);
	OPB:in std_logic_vector(0 to 127);
	CIN:in std_logic;
	PHI:in std_logic;
	SUM:out std_logic_vector(0 to 127);
	COUT:out std_logic
);
end component;
  component MULTIPLIER_18_18
    generic (mulpipe : integer := 0);
    port(MULTIPLICAND: in std_logic_vector(0 to 17);
         MULTIPLIER: in std_logic_vector(0 to 17);
         PHI: in std_ulogic;
	 holdn: in std_ulogic;
         RESULT: out std_logic_vector(0 to 63));
  end component;
  component MULTIPLIER_34_10
    port(MULTIPLICAND: in std_logic_vector(0 to 33);
         MULTIPLIER: in std_logic_vector(0 to 9);
         PHI: in std_logic;
         RESULT: out std_logic_vector(0 to 63));
  end component;
  component MULTIPLIER_34_18
    port(MULTIPLICAND: in std_logic_vector(0 to 33);
         MULTIPLIER: in std_logic_vector(0 to 17);
         PHI: in std_logic;
         RESULT: out std_logic_vector(0 to 63));
  end component;
  component MULTIPLIER_34_34
    port(MULTIPLICAND: in std_logic_vector(0 to 33);
         MULTIPLIER: in std_logic_vector(0 to 33);
         PHI: in std_logic;
         RESULT: out std_logic_vector(0 to 127));
  end component;
end;
------------------------------------------------------------
-- START: Entities used within the Modified Booth Recoding
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity FLIPFLOP is
port
(
	DIN: in std_logic;
	CLK: in std_logic;
	DOUT: out std_logic
);
end FLIPFLOP;

architecture FLIPFLOP of FLIPFLOP is
begin
process(CLK)
begin
	if(CLK='1')and(CLK'event)then
		DOUT <= DIN;
	end if;
end process;
end FLIPFLOP;

library ieee;
use ieee.std_logic_1164.all;
entity PP_LOW is
port
(
		ONEPOS, ONENEG, TWONEG: in std_logic;
		INA, INB: in std_logic;
		PPBIT: out std_logic
);
end PP_LOW;

architecture PP_LOW of PP_LOW is
begin
	PPBIT <= (ONEPOS and INA) or (ONENEG and INB) or TWONEG;
end PP_LOW;

library ieee;
use ieee.std_logic_1164.all;
entity PP_MIDDLE is
port
(
		ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
		INA, INB, INC, IND: in std_logic;
		PPBIT: out std_logic
);
end PP_MIDDLE;
architecture PP_MIDDLE of PP_MIDDLE is
begin
	PPBIT <= not((not(INA and TWOPOS)) and (not(INB and TWONEG)) and (not(INC and ONEPOS)) and (not(IND and ONENEG)));
end PP_MIDDLE;

library ieee;
use ieee.std_logic_1164.all;
entity PP_HIGH is
port
(
		ONEPOS, ONENEG, TWOPOS, TWONEG: in std_logic;
		INA, INB: in std_logic;
		PPBIT: out std_logic
);
end PP_HIGH;
architecture PP_HIGH of PP_HIGH is
begin
	PPBIT <= not ((INA and ONEPOS) or (INB and ONENEG) or (INA and TWOPOS) or (INB and TWONEG));
end PP_HIGH;

library ieee;
use ieee.std_logic_1164.all;
entity R_GATE is
port
(
		INA, INB, INC: in std_logic;
		PPBIT: out std_logic
);
end R_GATE;
architecture R_GATE of R_GATE is
begin
	PPBIT <= (not(INA and INB)) and INC;
end R_GATE;

library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
port
(
		INA, INB, INC: in std_logic;
		TWOPOS, TWONEG, ONEPOS, ONENEG: out std_logic
);
end DECODER;
architecture DECODER of DECODER is
begin
	TWOPOS <= not(not(INA and INB and (not INC)));
	TWONEG <= not(not((not INA) and (not INB) and INC));
	ONEPOS <= ((not INA) and INB and (not INC)) or ((not INC) and (not INB) and INA);
	ONENEG <= (INA and (not INB) and INC) or (INC and INB and (not INA));
end DECODER;

library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port
(
	DATA_A, DATA_B, DATA_C: in std_logic;
	SAVE, CARRY: out std_logic
);
end FULL_ADDER;
architecture FULL_ADDER of FULL_ADDER is
	signal TMP: std_logic;
begin
	TMP <= DATA_A xor DATA_B;
	SAVE <= TMP xor DATA_C;
	CARRY <= not((not (TMP and DATA_C)) and (not (DATA_A and DATA_B)));
end FULL_ADDER;

library ieee;
use ieee.std_logic_1164.all;
entity HALF_ADDER is
port
(
	DATA_A, DATA_B: in std_logic;
	SAVE, CARRY: out std_logic
);
end HALF_ADDER;
architecture HALF_ADDER of HALF_ADDER is
begin
	SAVE <= DATA_A xor DATA_B;
	CARRY <= DATA_A and DATA_B;
end HALF_ADDER;

library ieee;
use ieee.std_logic_1164.all;
entity INVBLOCK is
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end INVBLOCK;
architecture INVBLOCK_regular of INVBLOCK is
begin
	GOUT <= not GIN;
end INVBLOCK_regular;

library ieee;
use ieee.std_logic_1164.all;
entity XXOR1 is
port
(
	A,B,GIN,PHI:in std_logic;
	SUM:out std_logic
);
end XXOR1;
architecture XXOR_regular of XXOR1 is
begin
	SUM <= (not (A xor B)) xor GIN;
end XXOR_regular;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK0 is
port
(
	A,B,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK0;
architecture BLOCK0_regular of BLOCK0 is
begin
	POUT <= not(A or B);
	GOUT <= not(A and B);
end BLOCK0_regular;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1 is
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK1;
architecture BLOCK1_regular of BLOCK1 is
begin
	POUT <= not(PIN1 or PIN2);
	GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1_regular;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2 is
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end BLOCK2;
architecture BLOCK2_regular of BLOCK2 is
begin
	POUT <= not(PIN1 and PIN2);
	GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2_regular;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK1A is
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end BLOCK1A;
architecture BLOCK1A_regular of BLOCK1A is
begin
	GOUT <= not(GIN2 and (PIN2 or GIN1));
end BLOCK1A_regular;

library ieee;
use ieee.std_logic_1164.all;
entity BLOCK2A is
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end BLOCK2A;
architecture BLOCK2A_regular of BLOCK2A is
begin
	GOUT <= not(GIN2 or (PIN2 and GIN1));
end BLOCK2A_regular;

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity PRESTAGE_64 is
port
(
	A: in std_logic_vector(0 to 63);
	B: in std_logic_vector(0 to 63);
	CIN: in std_logic;
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 63);
	GOUT: out std_logic_vector(0 to 64)
);
end PRESTAGE_64;
architecture PRESTAGE of PRESTAGE_64 is
begin  -- PRESTAGE
U1:for I in 0 to 63 generate
	U11: BLOCK0 port map(A(I),B(I),PHI,POUT(I),GOUT(I+1));
end generate U1;
U2: INVBLOCK port map(CIN,PHI,GOUT(0));
end PRESTAGE;
-- The DBLC-tree: Level 0

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_0_64 is
port
(
	PIN: in std_logic_vector(0 to 63);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 62);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_0_64;

architecture DBLC_0 of DBLC_0_64 is

begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
	U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 64 generate
	U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;

-- The DBLC-tree: Level 1

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_1_64 is
port
(
	PIN: in std_logic_vector(0 to 62);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 60);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_1_64;

architecture DBLC_1 of DBLC_1_64 is

begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
	U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 64 generate
	U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;

-- The DBLC-tree: Level 2


library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_2_64 is
port
(
	PIN: in std_logic_vector(0 to 60);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 56);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_2_64;

architecture DBLC_2 of DBLC_2_64 is

begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
	U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 64 generate
	U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;

-- The DBLC-tree: Level 3

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_3_64 is
port
(
	PIN: in std_logic_vector(0 to 56);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 48);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_3_64;

architecture DBLC_3 of DBLC_3_64 is

begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
	U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 64 generate
	U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;

-- The DBLC-tree: Level 4

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_4_64 is
port
(
	PIN: in std_logic_vector(0 to 48);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 32);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_4_64;

architecture DBLC_4 of DBLC_4_64 is

begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
	U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 64 generate
	U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;

-- The DBLC-tree: Level 5

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity DBLC_5_64 is
port
(
	PIN: in std_logic_vector(0 to 32);
	GIN: in std_logic_vector(0 to 64);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 0);
	GOUT: out std_logic_vector(0 to 64)
);
end DBLC_5_64;

architecture DBLC_5 of DBLC_5_64 is

begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
	U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 64 generate
	U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;

library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.blocks.all;
entity XORSTAGE_64 is
port
(
	A: in std_logic_vector(0 to 63);
	B: in std_logic_vector(0 to 63);
	PBIT, PHI: in std_logic;
	CARRY: in std_logic_vector(0 to 64);
	SUM: out std_logic_vector(0 to 63);
	COUT: out std_logic
);
end XORSTAGE_64;
architecture XORSTAGE of XORSTAGE_64 is

begin -- XORSTAGE
U2:for I in 0 to 63 generate