debug.in.help

free hardware ip core about sparcv8,a soc cpu in vhdl

UART debugging
CONFIG_DEBUG_UART
  During simulation, the output from the UARTs is printed on the
  simulator console. Since the ratio between the system clock and
  UART baud-rate is quite high, simulating UART output will be very
  slow. If you say Y here, the UARTs will print a character as soon
  as it is stored in the transmitter data register. The transmitter
  ready flag will be permanently set, speeding up simulation. However,
  the output on the UART tx line will be garbled.  Has not impact on
  synthesis, but will cause the LEON test bench to fail.

FPU register tracing
CONFIG_DEBUG_FPURF
  If you say Y here, all writes to the floating-point unit register file
  will be printed on the simulator console.