axcelerator_components_full.vhd

来自「free hardware ip core about sparcv8,a so」· VHDL 代码 · 共 2,168 行 · 第 1/5 页

VHD
2,168 行
字号
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----------------------------------------------------------------------       Actel Axcelerator VITAL Library--       NAME: axcelerator.vhd--       DATE: Friday, February 11, 2005 ---------------------------------------------------------------------/library IEEE;use IEEE.std_logic_1164.all;--pragma translate_offuse IEEE.VITAL_Timing.all;--pragma translate_onpackage COMPONENTS is--pragma translate_offconstant DefaultTimingChecksOn : Boolean := True;constant DefaultXGenerationOn : Boolean := False;constant DefaultXon : Boolean := False;constant DefaultMsgOn : Boolean := True;--pragma translate_on------ Component ADD1 ------ component ADD1--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_S		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_S		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_FCI_S		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_A_FCO		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_FCO		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_FCI_FCO		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_FCI		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		FCI		: in    STD_ULOGIC;		S		: out    STD_ULOGIC;		FCO		: out    STD_ULOGIC); end component;------ Component AND2 ------ component AND2--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND2A ------ component AND2A--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND2B ------ component AND2B--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND3 ------ component AND3--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND3A ------ component AND3A--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND3B ------ component AND3B--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND3C ------ component AND3C--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND4 ------ component AND4--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND4A ------ component AND4A--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND4B ------ component AND4B--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND4C ------ component AND4C--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND4D ------ component AND4D--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND5A ------ component AND5A--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_E_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_E		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		E		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND5B ------ component AND5B--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_E_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_B		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_C		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_D		: VitalDelayType01 := (0.000 ns, 0.000 ns);		tipd_E		: VitalDelayType01 := (0.000 ns, 0.000 ns));--pragma translate_on    port(		A		: in    STD_ULOGIC;		B		: in    STD_ULOGIC;		C		: in    STD_ULOGIC;		D		: in    STD_ULOGIC;		E		: in    STD_ULOGIC;		Y		: out    STD_ULOGIC); end component;------ Component AND5C ------ component AND5C--pragma translate_off    generic(		TimingChecksOn:Boolean := True;		Xon: Boolean := False;		InstancePath: STRING :="*";		MsgOn: Boolean := True;		tpd_A_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_B_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_C_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_D_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tpd_E_Y		: VitalDelayType01 := (0.100 ns, 0.100 ns);		tipd_A		: VitalDelayType01 := (0.000 ns, 0.000 ns);
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axcelerator_components_full.vhd - 源码说明

本页面展示了「free hardware ip core about sparcv8,a soc cpu in vhdl」中的 axcelerator_components_full.vhd 源码文件，采用 VHDL 编程语言编写，共 2,168 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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