📄 orcacomp.vhd
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COMPONENT bbwPORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT obwPORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT ilvdsPORT( a : IN std_logic := 'X'; an: IN std_logic := 'X'; z : OUT std_logic );END COMPONENT;--COMPONENT olvdsPORT( a : IN std_logic := 'X'; z : OUT std_logic ; zn : OUT std_logic );END COMPONENT;--COMPONENT bbPORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT bbpdPORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT bbpuPORT( b: INOUT std_logic := 'X'; i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT ibPORT( i: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT ibpdPORT( i: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT ibpuPORT( i: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT obPORT( i: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT obzPORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT obzpdPORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT obzpuPORT( i: IN std_logic := 'X'; t: IN std_logic := 'X'; o: OUT std_logic);END COMPONENT;--COMPONENT dcsGENERIC( DCSMODE : String := "POS");PORT( clk0 : IN std_logic; clk1 : IN std_logic; sel : IN std_logic; dcsout : OUT std_logic);END COMPONENT;--component EPLLB generic( FIN : string := "100.0"; CLKI_DIV : string := "1"; CLKOP_DIV : string := "8"; CLKFB_DIV : string := "1"; FDEL : string := "1"; FB_MODE : string := "CLOCKTREE"; WAKE_ON_LOCK : string := "off"); port( CLKI : in STD_ULOGIC; RST : in STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKOP : out STD_ULOGIC; LOCK : out STD_ULOGIC );end component;--component EHXPLLB generic( FIN : string := "100.0"; CLKI_DIV : string := "1"; CLKOP_DIV : string := "1"; CLKFB_DIV : string := "1"; FDEL : string := "1"; FB_MODE : string := "CLOCKTREE"; CLKOK_DIV : string := "2"; WAKE_ON_LOCK : string := "off"; DELAY_CNTL : string := "STATIC"; PHASEADJ : string := "0"; DUTY : string := "4"); port( CLKI : in STD_ULOGIC; CLKFB : in STD_ULOGIC; RST : in STD_ULOGIC := '0'; DDAMODE : in STD_ULOGIC; DDAIZR : in STD_ULOGIC; DDAILAG : in STD_ULOGIC; DDAIDEL0 : in STD_ULOGIC; DDAIDEL1 : in STD_ULOGIC; DDAIDEL2 : in STD_ULOGIC; CLKOP : out STD_ULOGIC; CLKOS : out STD_ULOGIC; CLKOK : out STD_ULOGIC; LOCK : out STD_ULOGIC; DDAOZR : out STD_ULOGIC; DDAOLAG : out STD_ULOGIC; DDAODEL0 : out STD_ULOGIC; DDAODEL1 : out STD_ULOGIC; DDAODEL2 : out STD_ULOGIC);end component;--------Component ORCALUT4------component ORCALUT4 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; Z : out STD_ULOGIC );end component;------Component ORCALUT5------component ORCALUT5 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; Z : out STD_ULOGIC );end component;------Component ORCALUT6------component ORCALUT6 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; Z : out STD_ULOGIC );end component;------Component ORCALUT7------component ORCALUT7 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; G : in STD_ULOGIC; Z : out STD_ULOGIC );end component;------Component ORCALUT8------component ORCALUT8 generic( INIT : bit_vector); port( A : in STD_ULOGIC; B : in STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; E : in STD_ULOGIC; F : in STD_ULOGIC; G : in STD_ULOGIC; H : in STD_ULOGIC; Z : out STD_ULOGIC );end component;--component MULT2 port( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; B2 : in STD_ULOGIC; B3 : in STD_ULOGIC; CI : in STD_ULOGIC; P0 : out STD_ULOGIC; P1 : out STD_ULOGIC; CO : out STD_ULOGIC);end component;--component IDDRXB generic( REGSET : string := "RESET"); port( D : in STD_LOGIC; ECLK : in STD_LOGIC; SCLK : in STD_LOGIC; LSR : in STD_LOGIC; CE : in STD_LOGIC; DDRCLKPOL : in STD_LOGIC; QA : out STD_LOGIC; QB : out STD_LOGIC );end component;--component ODDRXB generic( REGSET : string := "RESET"); port( DA : in STD_LOGIC; DB : in STD_LOGIC; CLK : in STD_LOGIC; LSR : in STD_LOGIC; Q : out STD_LOGIC );end component;--component CCU2 generic ( inject1_0 : string := "YES"; inject1_1 : string := "YES"; init0: string := "0x0000"; init1: string := "0x0000" ); port ( A0,A1 : in std_ulogic; B0,B1 : in std_ulogic; C0,C1 : in std_ulogic; D0,D1 : in std_ulogic; CIN : in std_ulogic; S0,S1 : out std_ulogic; COUT0,COUT1 : out std_ulogic );end component;--component DQSBUFB generic(DEL_ADJ : string := "PLUS"; DEL_VAL : string := "0"); port( DQSI : in STD_LOGIC; CLK : in STD_LOGIC; READ : in STD_LOGIC; DQSDEL : in STD_LOGIC; DQSO : out STD_LOGIC; DDRCLKPOL : out STD_LOGIC; DQSC : out STD_LOGIC; PRMBDET : out STD_LOGIC );end component;--component DQSDLL generic(DEL_ADJ : string := "PLUS"; DEL_VAL : string := "0"; LOCK_SENSITIVITY : string := "LOW"); port( CLK : in STD_ULOGIC; RST : in STD_ULOGIC; UDDCNTL : in STD_ULOGIC; LOCK : out STD_ULOGIC; DQSDEL : out STD_ULOGIC );end component;---- 18x18 MULT for ECPcomponent MULT18X18 generic( REG_INPUTA_CLK : string := "NONE"; REG_INPUTA_CE : string := "CE0"; REG_INPUTA_RST : string := "RST0"; REG_INPUTB_CLK : string := "NONE"; REG_INPUTB_CE : string := "CE0"; REG_INPUTB_RST : string := "RST0"; REG_PIPELINE_CLK : string := "NONE"; REG_PIPELINE_CE : string := "CE0"; REG_PIPELINE_RST : string := "RST0"; REG_OUTPUT_CLK : string := "NONE"; REG_OUTPUT_CE : string := "CE0"; REG_OUTPUT_RST : string := "RST0"; REG_SIGNEDAB_0_CLK : string := "NONE"; REG_SIGNEDAB_0_CE : string := "CE0"; REG_SIGNEDAB_0_RST : string := "RST0"; REG_SIGNEDAB_1_CLK : string := "NONE"; REG_SIGNEDAB_1_CE : string := "CE0"; REG_SIGNEDAB_1_RST : string := "RST0"; SHIFT_IN_A : string := "FALSE"; SHIFT_IN_B : string := "FALSE"; GSR : string := "ENABLED"); port ( A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; A4 : in STD_ULOGIC; A5 : in STD_ULOGIC; A6 : in STD_ULOGIC; A7 : in STD_ULOGIC; A8 : in STD_ULOGIC; A9 : in STD_ULOGIC; A10 : in STD_ULOGIC; A11 : in STD_ULOGIC; A12 : in STD_ULOGIC; A13 : in STD_ULOGIC; A14 : in STD_ULOGIC; A15 : in STD_ULOGIC; A16 : in STD_ULOGIC; A17 : in STD_ULOGIC; SRIA0 : in STD_ULOGIC; SRIA1 : in STD_ULOGIC; SRIA2 : in STD_ULOGIC; SRIA3 : in STD_ULOGIC; SRIA4 : in STD_ULOGIC; SRIA5 : in STD_ULOGIC; SRIA6 : in STD_ULOGIC; SRIA7 : in STD_ULOGIC; SRIA8 : in STD_ULOGIC; SRIA9 : in STD_ULOGIC; SRIA10 : in STD_ULOGIC; SRIA11 : in STD_ULOGIC; SRIA12 : in STD_ULOGIC; SRIA13 : in STD_ULOGIC; SRIA14 : in STD_ULOGIC; SRIA15 : in STD_ULOGIC; SRIA16 : in STD_ULOGIC; SRIA17 : in STD_ULOGIC; B0 : in STD_ULOGIC; B1 : in STD_ULOGIC; B2 : in STD_ULOGIC; B3 : in STD_ULOGIC; B4 : in STD_ULOGIC; B5 : in STD_ULOGIC; B6 : in STD_ULOGIC; B7 : in STD_ULOGIC; B8 : in STD_ULOGIC; B9 : in STD_ULOGIC; B10 : in STD_ULOGIC; B11 : in STD_ULOGIC; B12 : in STD_ULOGIC; B13 : in STD_ULOGIC; B14 : in STD_ULOGIC; B15 : in STD_ULOGIC; B16 : in STD_ULOGIC; B17 : in STD_ULOGIC; SRIB0 : in STD_ULOGIC; SRIB1 : in STD_ULOGIC; SRIB2 : in STD_ULOGIC; SRIB3 : in STD_ULOGIC; SRIB4 : in STD_ULOGIC; SRIB5 : in STD_ULOGIC; SRIB6 : in STD_ULOGIC; SRIB7 : in STD_ULOGIC; SRIB8 : in STD_ULOGIC; SRIB9 : in STD_ULOGIC; SRIB10 : in STD_ULOGIC; SRIB11 : in STD_ULOGIC; SRIB12 : in STD_ULOGIC; SRIB13 : in STD_ULOGIC; SRIB14 : in STD_ULOGIC; SRIB15 : in STD_ULOGIC; SRIB16 : in STD_ULOGIC; SRIB17 : in STD_ULOGIC; SIGNEDAB : in STD_ULOGIC; CE0 : in STD_ULOGIC; CE1 : in STD_ULOGIC; CE2 : in STD_ULOGIC; CE3 : in STD_ULOGIC; CLK0 : in STD_ULOGIC; CLK1 : in STD_ULOGIC; CLK2 : in STD_ULOGIC; CLK3 : in STD_ULOGIC; RST0 : in STD_ULOGIC; RST1 : in STD_ULOGIC; RST2 : in STD_ULOGIC; RST3 : in STD_ULOGIC; SROA0 : out STD_ULOGIC; SROA1 : out STD_ULOGIC; SROA2 : out STD_ULOGIC; SROA3 : out STD_ULOGIC; SROA4 : out STD_ULOGIC; SROA5 : out STD_⌨️ 快捷键说明
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