orca_l.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL_V2 is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= TERMINAL_COUNT ; 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER ;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO V2 COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;

entity FLAG_LOGIC_V2 is
 	generic (
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
                GLOBAL_RST : in STD_LOGIC ;
		FIFO_CAP   : in integer ; 	
                FIFO_PTR   : in integer ;
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC_V2;

architecture LATTICE_BEHAV of FLAG_LOGIC_V2 is

begin 
--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL_EMPTY_AMEMPTY: process  (GLOBAL_RST, FIFO_CAP, FIFO_PTR)

begin

	if GLOBAL_RST = '1'  then 
	    FULL_D    <= '0';
	    AMFULL_D  <= '0';
	    EMPTY_D   <= '0';
            AMEMPTY_D <= '0';
	else
		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH) then
		     FULL_D <= '1';
		else
		     FULL_D <= '0';	
	        end if;

		if (FIFO_CAP - FIFO_PTR < WDATA_WIDTH + AMFULL_X * WDATA_WIDTH) then
		     AMFULL_D <= '1';
		else
		     AMFULL_D <= '0';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH) then
		     EMPTY_D <= '0';
	        else
		     EMPTY_D <= '1';	
	        end if;

		if (FIFO_PTR < RDATA_WIDTH + AMEMPTY_Y * RDATA_WIDTH) then
		     AMEMPTY_D <= '0';
	        else
		     AMEMPTY_D <= '1';	
		end if;
	end if;

end process FULL_AMFULL_EMPTY_AMEMPTY;

end LATTICE_BEHAV;


-- ************************************************************************
-- FIFO V2 Main Body 
-- READ_POINTER_CTRL_V2
-- WRITE_POINTER_CTRL_V2
-- FLAG_LOGIC_V2 
-- SC_BRAM_16K
-- ************************************************************************
-- ************************************************************************
-- Top Design Entity definition  
-- ************************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SC_FIFO_V2_16K_L is

  generic (
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   8;
        RDATA_WIDTH    : integer :=  64;
        ALMOST_FULL_X  : integer :=   2;
        ALMOST_EMPTY_Y : integer :=   2;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_V2_16K_L ;

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_FIFO_V2_16K_L is

---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
 function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
 
 begin 
    vTRANS := INPUT_STRING;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i) = '1') then
        vDATA_STD_VEC(i-1) := '1';
      elsif ( vTRANS(i) ='0') then
        vDATA_STD_VEC(i-1) := '0';
      end if;  
    end loop;
  return vDATA_STD_VEC; 	  
 end TO_STD_VECTOR; 

---------------------------------------------------------
-- Components Definition
---------------------------------------------------------

component SC_BRAM_16K_L

  generic (
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0)
        ); 
 end component;

 component READ_POINTER_CTRL_V2

 	generic (
                RPOINTER_WIDTH : integer := 9
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);
                GLOBAL_RST     : in STD_LOGIC ;
                RESET_RP       : in STD_LOGIC ;
                READ_EN        : in STD_LOGIC ;
                READ_CLK       : in STD_LOGIC ;
                EMPTY_FLAG     : in STD_LOGIC ;
                READ_POINTER   : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
             );
 end component;

 component WRITE_POINTER_CTRL_V2
 	generic (
		WPOINTER_WIDTH : integer := 9;
		WDATA_WIDTH    : integer := 32
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);
                GLOBAL_RST     : in STD_LOGIC ;
                WRITE_EN       : in STD_LOGIC ;
                WRITE_CLK      : in STD_LOGIC ;
                FULL_FLAG      : in STD_LOGIC ;
                WRITE_POINTER  : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
		);
 end component;
		
 component FLAG_LOGIC_V2
 	generic (
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X       : integer := 1;
                AMEMPTY_Y      : integer := 1
		);
	port (
                GLOBAL_RST : in STD_LOGIC ;
		FIFO_CAP   : in integer ; 	
                FIFO_PTR   : in integer ;
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
 end component;
 -- Signal Declaration
 
 signal WE_node      :  STD_LOGIC := 'X';
 signal WCLK_node    :  STD_LOGIC := 'X';
 signal RST_node     :  STD_LOGIC := 'X';
 signal RPRST_node   :  STD_LOGIC := 'X';
 signal RE_node      :  STD_LOGIC := 'X';
 signal RCLK_node    :  STD_LOGIC := 'X';
 signal FULLIN_node  :  STD_LOGIC := 'X';
 signal EMPTYIN_node :  STD_LOGIC := 'X';
 signal DI_node      :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');

 signal DI_reg       :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => 'X');
 signal WE_reg       :  STD_LOGIC := 'X';  
 signal RE_reg       :  STD_LOGIC := 'X';  
 signal FULLIN_reg   :  STD_LOGIC := 'X';
 signal EMPTYIN_reg  :  STD_LOGIC := 'X';

 signal FULL_node    :  STD_LOGIC := 'X';
 signal EMPTY_node   :  STD_LOGIC := 'X';
 signal AMFULL_node  :  STD_LOGIC := 'X';
 signal AMEMPTY_node :  STD_LOGIC := 'X';
 signal DO_node      :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => 'X');

 signal TC_W_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => 'X'); 
 signal TC_R_node      :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0) := (others => 'X'); 

 signal FULL_reg     :  STD_LOGIC := 'X';
 signal EMPTY_reg    :  STD_LOGIC := 'X';
 signal AMFULL_reg   :  STD_LOGIC := 'X';
 signal AMEMPTY_reg  :  STD_LOGIC := 'X';

 signal RP_node      :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0)  := (others => 'X');
 signal WP_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0)  := (others => '0');
 signal GND_sig      :  STD_LOGIC := 'X';

--QQ FIFOV2
 signal FIFO_capacity : integer := 0; 	
 signal FIFO_pointer  : integer := 0;
-- architecture

 begin
  FIFO_capacity <= (TERMINAL_COUNT + 1) * WDATA_WIDTH; 	

  GND_sig      <= '0';
  WE_node      <= WE and not (FULL_node);
  WCLK_node    <= WCLK;
  RST_node     <= RST;
  RPRST_node   <= RPRST;
  RE_node      <= RE;
  RCLK_node    <= RCLK;
  FULLIN_node  <= FULLIN;
  EMPTYIN_node <= EMPTYIN;
  DI_node      <= DI;

  TC_W_node      <= CONV_STD_LOGIC_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
  TC_R_node      <= CONV_STD_LOGIC_VECTOR((TERMINAL_COUNT+1)*(WDATA_WIDTH/RDATA_WIDTH)-1,RADDR_WIDTH);


  --FULL    <= FULL_node;
  FULL    <= FULL_node when (RE_node = '0') else FULL_reg;
  --AMFULL  <= AMFULL_node;
  AMFULL  <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
  EMPTY   <= not EMPTY_node;
  AMEMPTY <= not AMEMPTY_node;
  
  DO <= DO_node;    

-- Register Port DI inputs
  register_DI_inputs: process (RST_node, WCLK_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WE_node = '1') then
        DI_reg <= DI_node after 1 ps;
      end if;
    end if;
  end process register_DI_inputs;   

-- Register flag inputs
  register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULLIN_reg  <= '0';
      EMPTYIN_reg <= '0';
      WE_reg <= '0';  
      RE_reg <= '0';  
    else
    
      if (WCLK_node'event and WCLK_node = '1') then
          WE_reg <= WE_node and not FULL_reg;  --Fix DTS14659
          --WE_reg <= WE_node;  
        if (WE_node = '1') then
          FULLIN_reg <= FULLIN_node;
        end if;
      end if;

      if (RCLK_node'event and RCLK_node = '1') then
          RE_reg <= RE_node and EMPTY_reg;  
        if (RE_node = '1') then
          EMPTYIN_reg <= EMPTYIN_node;
        end if;
      end if;

    end if;
  end process register_flag_inputs; 
  
-- Register flag outputs
  register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULL_node    <= '0';
      AMFULL_node  <= '0';
      EMPTY_node   <= '0';
      AMEMPTY_node <= '0';
    else
      if (WCLK_node'event and WCLK_node = '1') then
        FULL_node <= FULL_reg;
        AMFULL_node <= AMFULL_reg;
      end if;
      if (RCLK_node'event and RCLK_node = '1') then
        EMPTY_node <= EMPTY_reg;
        AMEMPTY_node <= AMEMPTY_reg;