orca_l.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

---------------------------------------------------------
 function INT_TO_VEC ( INPUT_INT : integer; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: integer := 0;
   variable vQUOTIENT: integer := 0;
 
 begin 
    vQUOTIENT := INPUT_INT;

    for i in 0 to INPUT_LENGTH -1 loop
	vTRANS := 0;
	while vQUOTIENT >1 loop
	    vQUOTIENT := vQUOTIENT - 2;
            vTRANS := vTRANS + 1;
	end loop;
        case vQUOTIENT is
              when 1 =>
                 vDATA_STD_VEC(i) := '1';
              when 0 =>
                 vDATA_STD_VEC(i) := '0';
              when others =>
                 null;
        end case;
        vQUOTIENT := vTRANS; 
    end loop;
  return vDATA_STD_VEC; 	  
 end INT_TO_VEC; 
---------------------------------------------------------
-- Components Definition
---------------------------------------------------------

component SC_BRAM_16K_L_SYNC

  generic (
         WADDR_WIDTH_A : integer := 14;
         RADDR_WIDTH_A : integer := 12;
         WADDR_WIDTH_B : integer := 14;
         RADDR_WIDTH_B : integer := 12;
         WDATA_WIDTH_A : integer := 1;
         RDATA_WIDTH_A : integer := 4;
         WDATA_WIDTH_B : integer := 1;
         RDATA_WIDTH_B : integer := 4;
         ARRAY_SIZE    : integer := 16384;
         MEM_INIT_FLAG : integer := 0;  
         MEM_INIT_FILE : string  := "mem_init_file"

          );

  port (
         WADA : in  STD_LOGIC_VECTOR (WADDR_WIDTH_A -1 downto 0);
         WEA  : in  STD_LOGIC ;
         WDA  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_A -1 downto 0);
         RADA : in  STD_LOGIC_VECTOR (RADDR_WIDTH_A -1 downto 0);
         REA  : in  STD_LOGIC ;
         RDA  : out STD_LOGIC_VECTOR (RDATA_WIDTH_A -1 downto 0);
         
         WADB : in  STD_LOGIC_VECTOR (WADDR_WIDTH_B -1 downto 0);
         WEB  : in  STD_LOGIC;
         WDB  : in  STD_LOGIC_VECTOR (WDATA_WIDTH_B -1 downto 0);
         RADB : in  STD_LOGIC_VECTOR (RADDR_WIDTH_B -1 downto 0);
         REB  : in  STD_LOGIC;
         RDB  : out STD_LOGIC_VECTOR (RDATA_WIDTH_B -1 downto 0);
	 WCLK : in  STD_LOGIC;
	 RCLK : in  STD_LOGIC
        ); 
 end component;

 component READ_POINTER_CTRL

 	generic (
                RPOINTER_WIDTH : integer := 9
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
                GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
                EMPTY_FLAG   : in STD_LOGIC ;
                READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
             );
 end component;

 component WRITE_POINTER_CTRL
 	generic (
		WPOINTER_WIDTH : integer := 9;
		WDATA_WIDTH : integer := 32
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
                GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG    : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
		);
 end component;
		
 component FLAG_LOGIC
 	generic (
                WPOINTER_WIDTH : integer := 9;
                RPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
                R_POINTER  : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0);
                W_POINTER  : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0);
                GLOBAL_RST : in STD_LOGIC ;
                READ_EN    : in STD_LOGIC ;
                READ_CLK   : in STD_LOGIC ;
                WRITE_EN   : in STD_LOGIC ;
                WRITE_CLK  : in STD_LOGIC ; 
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
 end component;
 -- Signal Declaration
 
 signal WE_node      :  STD_LOGIC := '0';
 signal WCLK_node    :  STD_LOGIC := '0';
 signal RST_node     :  STD_LOGIC := '0';
 signal RPRST_node   :  STD_LOGIC := '0';
 signal RE_node      :  STD_LOGIC := '0';
 signal RCLK_node    :  STD_LOGIC := '0';
 signal FULLIN_node  :  STD_LOGIC := '0';
 signal EMPTYIN_node :  STD_LOGIC := '0';
 signal DI_node      :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');

 signal DI_reg       :  STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0) := (others => '0');
 signal FULLIN_reg   :  STD_LOGIC := '0';
 signal EMPTYIN_reg  :  STD_LOGIC := '0';

 signal FULL_node    :  STD_LOGIC := '0';
 signal EMPTY_node   :  STD_LOGIC := '0';
 signal AMFULL_node  :  STD_LOGIC := '0';
 signal AMEMPTY_node :  STD_LOGIC := '0';
 signal DO_node      :  STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0) := (others => '0');

 signal TC_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0) := (others => '0'); 

 signal FULL_reg     :  STD_LOGIC := '0';
 signal EMPTY_reg    :  STD_LOGIC := '0';
 signal AMFULL_reg   :  STD_LOGIC := '0';
 signal AMEMPTY_reg  :  STD_LOGIC := '0';

 signal RP_node      :  STD_LOGIC_VECTOR (RADDR_WIDTH -1 downto 0)  := (others => '0');
 signal WP_node      :  STD_LOGIC_VECTOR (WADDR_WIDTH -1 downto 0)  := (others => '0');

 signal GND_sig      :  STD_LOGIC := '0';
-- architecture

 begin

  GND_sig      <= '0';
  WE_node      <= WE and not(FULL_node);
  WCLK_node    <= WCLK;
  RST_node     <= RST;
  RPRST_node   <= RPRST;
  RE_node      <= RE and EMPTY_node;
  RCLK_node    <= RCLK;
  FULLIN_node  <= FULLIN;
  EMPTYIN_node <= EMPTYIN;
  DI_node      <= DI;
  --TC_node      <= TO_STD_VECTOR(TERMINAL_COUNT,WADDR_WIDTH);
  TC_node      <= INT_TO_VEC(TERMINAL_COUNT,WADDR_WIDTH);

  --FULL    <= FULL_node;
  FULL    <= FULL_node when (RE_node = '0') else FULL_reg;
  --AMFULL  <= AMFULL_node;
  AMFULL  <= AMFULL_node when (RE_node = '0') else AMFULL_reg;
  EMPTY   <= not EMPTY_node;
  AMEMPTY <= not AMEMPTY_node;

  DO <= DO_node;    

-- Register Port DI inputs
  register_DI_inputs: process (RST_node, WCLK_node)
  begin
    if (RST_node = '1') then
      DI_reg <= (others =>'0');
    elsif (WCLK_node'event and WCLK_node = '1') then
      if (WE_node = '1') then
        DI_reg <= DI_node after 1 ps;
      end if;
    end if;
  end process register_DI_inputs;   

-- Register flag inputs
  register_flag_inputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULLIN_reg  <= '0';
      EMPTYIN_reg <= '0';
    else
    
      if (WCLK_node'event and WCLK_node = '1') then
      --   WE_reg <= WE_node and not (FULL_reg);  --QQ
        if (WE_node = '1') then
          FULLIN_reg <= FULLIN_node;
        end if;
      end if;

      if (RCLK_node'event and RCLK_node = '1') then
       --  RE_reg <= RE_node and EMPTY_reg;  --QQ
        if (RE_node = '1') then
          EMPTYIN_reg <= EMPTYIN_node;
        end if;
      end if;

    end if;
  end process register_flag_inputs; 
  
-- Register flag outputs
  register_flag_outputs: process (RST_node, WCLK_node, RCLK_node)
  begin
    if (RST_node = '1') then
      FULL_node    <= '0';
      AMFULL_node  <= '0';
      EMPTY_node   <= '0';
      AMEMPTY_node <= '0';
    else
      if (WCLK_node'event and WCLK_node = '1') then
        FULL_node <= FULL_reg;
        AMFULL_node <= AMFULL_reg;
      end if;
      if (RCLK_node'event and RCLK_node = '1') then
        EMPTY_node <= EMPTY_reg;
        AMEMPTY_node <= AMEMPTY_reg;
      end if; 
    end if;
  end process register_flag_outputs; 

-- READ_POINTER_CTRL instance for FIFO
  FIFO_RPC_INST: READ_POINTER_CTRL
        generic map (
		RPOINTER_WIDTH => RADDR_WIDTH
		)
        port map (
		TERMINAL_COUNT => TC_node,
		GLOBAL_RST   => RST_node,
                RESET_RP     => RPRST_node,
                READ_EN      => RE_node,
                READ_CLK     => RCLK_node,
                EMPTY_FLAG   => EMPTY_reg,
                READ_POINTER => RP_node
	     );
 
-- WRITE_POINTER_CTRL instance for FIFO
  FIFO_WPC_INST: WRITE_POINTER_CTRL
        generic map (
                WPOINTER_WIDTH => WADDR_WIDTH, 
                WDATA_WIDTH    => WDATA_WIDTH
		)
        port map (
		TERMINAL_COUNT => TC_node,
		GLOBAL_RST     => RST_node,
                WRITE_EN       => WE_node,
                WRITE_CLK      => WCLK_node,
                FULL_FLAG      => FULL_reg,
                WRITE_POINTER  => WP_node
		);
 
-- FLAG_LOGIC instance for FIFO
  FIFO_FL_INST: FLAG_LOGIC
           generic map (
                WPOINTER_WIDTH => WADDR_WIDTH, 
                RPOINTER_WIDTH => RADDR_WIDTH, 
                WDATA_WIDTH    => WDATA_WIDTH, 
                RDATA_WIDTH    => RDATA_WIDTH, 
                AMFULL_X       => ALMOST_FULL_X, 
                AMEMPTY_Y      => ALMOST_EMPTY_Y
		)
           port map(
   		TERMINAL_COUNT => TC_node,
		R_POINTER     => RP_node, 
                W_POINTER     => WP_node, 
                GLOBAL_RST    => RST_node, 
                READ_EN       => RE_node, 
                READ_CLK      => RCLK_node, 
                WRITE_EN      => WE_node, 
                WRITE_CLK     => WCLK_node, 
                FULL_D        => FULL_reg, 
                EMPTY_D       => EMPTY_reg, 
                AMFULL_D      => AMFULL_reg, 
                AMEMPTY_D     => AMEMPTY_reg 
	);

-- BRAM instance for FIFO 
  FIFO_BRAM_INST: SC_BRAM_16K_L_SYNC

    generic map(
         WADDR_WIDTH_A  => WADDR_WIDTH, 
         RADDR_WIDTH_A  => RADDR_WIDTH, 
         WADDR_WIDTH_B  => WADDR_WIDTH, 
         RADDR_WIDTH_B  => RADDR_WIDTH, 
         WDATA_WIDTH_A  => WDATA_WIDTH, 
         RDATA_WIDTH_A  => RDATA_WIDTH, 
         WDATA_WIDTH_B  => WDATA_WIDTH, 
         RDATA_WIDTH_B  => RDATA_WIDTH, 
         ARRAY_SIZE     => open,
    	 MEM_INIT_FLAG  => MEM_INIT_FLAG,  
	 MEM_INIT_FILE  => MEM_INIT_FILE

       )
    port map (
         WADA => WP_node,
         WEA  => WE_node,
         WDA  => DI_node, 
         RADA => RP_node,
         REA  => RE_node,
         RDA  => DO_node, 
         
         WADB => WP_node, 
         WEB  => GND_sig, 
         WDB  => DI_node, 
         RADB => RP_node, 
         REB  => GND_sig, 
         RDB  => open,
	 WCLK => WCLK_node,
	 RCLK => RCLK_node
      );

end LATTICE_BEHAV;

-- ************************************************************************
--
--  FIFO V2: Behavioral Model
-- ************************************************************************
--
--  Filename:  SC_FIFO_V2.vhd
--  Description: FIFO behavioral model. 

-- ************************************************************************
-- FIFO COMPONENTS READ_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL_V2 is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL_V2;

architecture LATTICE_BEHAV of READ_POINTER_CTRL_V2 is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

        s_READ_POINTER <= TERMINAL_COUNT; 

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
		  
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL_V2
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL_V2 is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);