orca_l.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

        ) then
      assert false
        report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
        severity warning;
    end if;  

  -- MEM Operation	
    if (WEA_node = '1') then
        v_MEM((v_WADDR_A*WDATA_WIDTH_A + WDATA_WIDTH_A -1) downto (v_WADDR_A*WDATA_WIDTH_A)) := WDA_node;
    end if;

    if (WEB_node = '1') then
        v_MEM((v_WADDR_B*WDATA_WIDTH_B + WDATA_WIDTH_B -1) downto (v_WADDR_B*WDATA_WIDTH_B)) := WDB_node;
    end if;

    if (REA_node = '1') then
       RDA_node <= v_MEM((v_RADDR_A*RDATA_WIDTH_A + RDATA_WIDTH_A -1) downto (v_RADDR_A*RDATA_WIDTH_A));
--    else
--       RDA_node <= ( others => 'X');
    end if;
    
    if (REB_node = '1') then
       RDB_node <= v_MEM((v_RADDR_B*RDATA_WIDTH_B + RDATA_WIDTH_B -1) downto (v_RADDR_B*RDATA_WIDTH_B));
--    else
--       RDB_node <= ( others => 'X');
    end if;
    
  end process KERNEL_BEHAV;
    
end LATTICE_BEHAV;



---*************  SC_FIFO_L **************************
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity READ_POINTER_CTRL is
	generic (
              RPOINTER_WIDTH : integer := 9
		);
	port (
                TERMINAL_COUNT : in STD_LOGIC_VECTOR(RPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST   : in STD_LOGIC ;
                RESET_RP     : in STD_LOGIC ;
                READ_EN      : in STD_LOGIC ;
                READ_CLK     : in STD_LOGIC ;
	        EMPTY_FLAG   : in STD_LOGIC ;
		READ_POINTER : out STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0)
	     );
end READ_POINTER_CTRL;

architecture LATTICE_BEHAV of READ_POINTER_CTRL is

  signal s_READ_POINTER : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');

begin

  READ_POINTER <= s_READ_POINTER; 

process  (GLOBAL_RST, RESET_RP, READ_EN, READ_CLK)

	variable v_READ_POINTER: STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0');

begin

	if GLOBAL_RST = '1'  or RESET_RP = '1' then 

          s_READ_POINTER <= (others => '0');

	elsif (READ_CLK'EVENT and READ_CLK = '1') then
		if (READ_EN = '1' and EMPTY_FLAG = '1') then
                  v_READ_POINTER := s_READ_POINTER + '1';
                else  
                  v_READ_POINTER := s_READ_POINTER;
		end if;

		if (v_READ_POINTER = TERMINAL_COUNT + 1) then
		   s_READ_POINTER <= (others => '0');
		else
		   s_READ_POINTER <= v_READ_POINTER;
		end if;
	end if;

end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS WRITE_POINTER_CTRL
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity WRITE_POINTER_CTRL is
        generic (
                WPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH : integer := 32
		);
        port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0);--QQ
		GLOBAL_RST    : in STD_LOGIC ;
                WRITE_EN      : in STD_LOGIC ;
                WRITE_CLK     : in STD_LOGIC ;
                FULL_FLAG     : in STD_LOGIC ;
                WRITE_POINTER : out STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0)
            
	     );
end WRITE_POINTER_CTRL;

architecture LATTICE_BEHAV of WRITE_POINTER_CTRL is

 signal s_WRITE_POINTER : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin 

  WRITE_POINTER <= s_WRITE_POINTER;

  process  (GLOBAL_RST, WRITE_EN, WRITE_CLK)

    variable v_WRITE_POINTER: STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0');

begin
	if GLOBAL_RST = '1'  then 
		s_WRITE_POINTER <= (others => '0'); 

	elsif (WRITE_CLK'EVENT and WRITE_CLK = '1') then
		if (WRITE_EN = '1' and FULL_FLAG /= '1') then
		   v_WRITE_POINTER := s_WRITE_POINTER + '1';
                else
		   v_WRITE_POINTER := s_WRITE_POINTER ;
                end if; 

		if (v_WRITE_POINTER = TERMINAL_COUNT + 1) then
		   s_WRITE_POINTER <= (others => '0');
		else
		   s_WRITE_POINTER <= v_WRITE_POINTER;
		end if;
	end if;
end process;
end LATTICE_BEHAV;

-- ************************************************************************
-- FIFO COMPONENTS FLAG LOGIC
-- ************************************************************************
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity FLAG_LOGIC is
 	generic (
                WPOINTER_WIDTH : integer := 9;
                RPOINTER_WIDTH : integer := 9;
                WDATA_WIDTH    : integer := 32; 
                RDATA_WIDTH    : integer := 32; 
                AMFULL_X      : integer := 1;
                AMEMPTY_Y     : integer := 1
		);
	port (
		TERMINAL_COUNT : in STD_LOGIC_VECTOR(WPOINTER_WIDTH -1 downto 0) := (others => '0');--QQ
		R_POINTER  : in STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0) := (others => '0');
                W_POINTER  : in STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0');
                GLOBAL_RST : in STD_LOGIC ;
                READ_EN    : in STD_LOGIC ;
                READ_CLK   : in STD_LOGIC ;
                WRITE_EN   : in STD_LOGIC ;
                WRITE_CLK  : in STD_LOGIC ; 
                FULL_D     : out STD_LOGIC ;
                EMPTY_D    : out STD_LOGIC ;
                AMFULL_D   : out STD_LOGIC ;
                AMEMPTY_D  : out STD_LOGIC 
	);
end FLAG_LOGIC;

architecture LATTICE_BEHAV of FLAG_LOGIC is
--------------------------------------------------------------------------
-- Function: Valid_Address 
-- Description: 
--------------------------------------------------------------------------
function Valid_Pointer (
    IN_ADDR : in STD_LOGIC_VECTOR
 ) return BOOLEAN is

    variable v_Valid_Flag : BOOLEAN := TRUE;
 
begin

    for i in IN_ADDR'high downto IN_ADDR'low loop
        if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
            v_Valid_Flag := FALSE;
        end if;
    end loop;

    return v_Valid_Flag;
end Valid_Pointer;

--------------------------------------------------------------------------
-- Function: Calculate_Offset 
-- Description: 
--------------------------------------------------------------------------
function Calculate_Offset (
    IN_TC : in  STD_LOGIC_VECTOR;
    TC_LENGTH: in INTEGER
 ) return STD_LOGIC_VECTOR is

    variable vTC_FULL: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '1');
    variable vTC_TEMP: STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
    variable vOFFSET : STD_LOGIC_VECTOR (TC_LENGTH -1 downto 0) := (others => '0');
begin
    vTC_TEMP := IN_TC;
    vOFFSET := vTC_FULL-vTC_TEMP;
    return vOFFSET;
end Calculate_Offset;
   
begin 

--------------------------------------------------------------------------
-- Function: Main Process 
-- Description: 
--------------------------------------------------------------------------
FULL_AMFULL: process  (GLOBAL_RST, WRITE_EN, WRITE_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    --variable v_WP_Check_FULL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL_TMP1 : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_FULL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ
    variable v_WP_Check_AMFL : STD_LOGIC_VECTOR (WPOINTER_WIDTH -1 downto 0) := (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_WP_Valid_Flag = TRUE) then
             v_WP_Check_AMFL_TMP := W_POINTER + AMFULL_X + 1;
        end if;

        v_WP_Check_AMFL_TMP1 := v_WP_Check_AMFL_TMP + Calculate_Offset(TERMINAL_COUNT, WPOINTER_WIDTH);

	if ( v_WP_Valid_Flag = TRUE and W_POINTER = TERMINAL_COUNT ) then 
	    v_WP_Check_FULL := (others => '0');
	elsif( v_WP_Valid_Flag = TRUE ) then 
	    v_WP_Check_FULL := W_POINTER + 1; 
	end if;

	if GLOBAL_RST = '1'  then 
	    FULL_D <= '0';
	    AMFULL_D <= '0';

	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then

	    if R_POINTER = v_WP_Check_FULL then
	     FULL_D <= '1';
            else
	     FULL_D <= '0';	
            end if;

            if (W_POINTER > R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
                if v_WP_Check_AMFL_TMP1 >= R_POINTER then
	         AMFULL_D <= '1';
	        else
	         AMFULL_D <= '0'; 	
	        end if; 
              else 
	         AMFULL_D <= '0'; 	
              end if;    
            elsif (W_POINTER < R_POINTER) then
	      if (v_WP_Check_AMFL_TMP1 < W_POINTER) then
	         AMFULL_D <= '1';
	      elsif (v_WP_Check_AMFL_TMP >= R_POINTER) then
	         AMFULL_D <= '1';
	      else 
	         AMFULL_D <= '0'; 	
	      end if; 
            end if;    

        end if;

end process FULL_AMFULL;

EMPTY_AMEMPTY: process  (GLOBAL_RST, READ_EN, READ_CLK, W_POINTER, R_POINTER)
    variable v_WP_Valid_Flag : boolean := TRUE;
    variable v_RP_Valid_Flag : boolean := TRUE;
    variable v_RP_Check_EMPT_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET_TMP1 : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    --variable v_RP_Check_EMPT : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ
    variable v_RP_Check_AMET : STD_LOGIC_VECTOR (RPOINTER_WIDTH -1 downto 0):= (others => '0'); --QQ

begin
        v_WP_Valid_Flag := Valid_Pointer(W_POINTER);	
        v_RP_Valid_Flag := Valid_Pointer(R_POINTER);
	if( v_RP_Valid_Flag = TRUE and v_WP_Valid_Flag = TRUE) then
	    v_RP_Check_AMET_TMP := R_POINTER + AMEMPTY_Y ; -- Different from TSPEC QQ 07 17,2002
        end if;
        v_RP_Check_AMET_TMP1 := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);

	if GLOBAL_RST = '1'  then 
	  EMPTY_D <= '0';
	  AMEMPTY_D <= '0';
	elsif( v_WP_Valid_Flag = TRUE and v_RP_Valid_Flag = TRUE) then
            if R_POINTER  = W_POINTER then   -- Different from TSPEC QQ 07 17,2002
                    EMPTY_D <= '0';
            else
                    EMPTY_D <= '1';
            end if;

	    
	    if (W_POINTER < R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	          v_RP_Check_AMET := v_RP_Check_AMET_TMP + Calculate_Offset(TERMINAL_COUNT, RPOINTER_WIDTH);
                if v_RP_Check_AMET >= W_POINTER then
	         AMEMPTY_D <= '0';
	        else
	         AMEMPTY_D <= '1'; 	
	        end if; 
              else 
	         AMEMPTY_D <= '1'; 	
              end if;    
            elsif (W_POINTER > R_POINTER) then
	      if (v_RP_Check_AMET_TMP1 < R_POINTER) then
	         AMEMPTY_D <= '0';
	      elsif (v_RP_Check_AMET_TMP >= W_POINTER) then
	         AMEMPTY_D <= '0';
	      else 
	         AMEMPTY_D <= '1'; 	
	      end if; 
            elsif (W_POINTER = R_POINTER) then
              AMEMPTY_D <= '0';
            end if;    
       end if;
end process EMPTY_AMEMPTY;

end LATTICE_BEHAV;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
---USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

--LIBRARY SC_LIB;
--USE SC_LIB.SC_FIFO_COMPS.ALL;

entity SC_FIFO_16K_L is 
  generic (
  	TERMINAL_COUNT : integer := 511; --QQ: Word number < 2**WADDR_WIDTH
	WADDR_WIDTH    : integer :=   9;
        WDATA_WIDTH    : integer :=  32;
        RADDR_WIDTH    : integer :=   9;
        RDATA_WIDTH    : integer :=  32;
        ALMOST_FULL_X  : integer :=   1;
        ALMOST_EMPTY_Y : integer :=   1;
        MEM_INIT_FLAG  : integer :=   0;  
        MEM_INIT_FILE  : string  := "mem_init_file"

         );

  port (
        WE      : in STD_LOGIC ;
        WCLK    : in STD_LOGIC ;
        RST     : in STD_LOGIC ;
        RPRST   : in STD_LOGIC ;
        RE      : in STD_LOGIC ;
        RCLK    : in STD_LOGIC ;
        FULLIN  : in STD_LOGIC ;
        EMPTYIN : in STD_LOGIC ;
        DI      : in STD_LOGIC_VECTOR (WDATA_WIDTH -1 downto 0);

        FULL    : out STD_LOGIC ;
        EMPTY   : out STD_LOGIC ;
        AMFULL  : out STD_LOGIC ;
        AMEMPTY : out STD_LOGIC ;
        DO      : out STD_LOGIC_VECTOR (RDATA_WIDTH -1 downto 0)

        ); 

end SC_FIFO_16K_L; 

-- ************************************************************************
-- architecture
-- ************************************************************************

architecture LATTICE_BEHAV of SC_FIFO_16K_L is 

---------------------------------------------------------
-- Function: TO_STD_VECTOR
---------------------------------------------------------
 function TO_STD_VECTOR ( INPUT_STRING : string; INPUT_LENGTH: integer)
 return std_logic_vector is

   variable vDATA_STD_VEC: std_logic_vector(INPUT_LENGTH -1 downto 0) := (others => '0');
   variable vTRANS: string(INPUT_LENGTH downto 1) := (others => '0');
 
 begin 
    vTRANS := INPUT_STRING;

    for i in INPUT_LENGTH downto 1 loop
      if (vTRANS(i) = '1') then
        vDATA_STD_VEC(i-1) := '1';
      elsif ( vTRANS(i) ='0') then
        vDATA_STD_VEC(i-1) := '0';
      end if;  
    end loop;
  return vDATA_STD_VEC; 	  
 end TO_STD_VECTOR; 

---------------------------------------------------------
-- Function: INT_TO_VEC