othertest_1.c

该程序实现的是一个在织布厂用的提花机程序

#include "wea_dos.h"
void FpgaPCBTest(char* info)
{
	unsigned short  p=FPGA_TEST;
	ERROR_CODE err;
	BYTE d;
	BYTE ram_data[8];
	int i;
	BOOL bOK=1;
	char info1[500];
	char* send_table[]={"","","","SCLK_O","SDATA_O","LATCH_O","ENABLE_O","SCLK_O","SDATA_O","LATCH_O",
		"ZONE_A","ZONE_B","JOB_END","COL1","COL2","COL3","COL4","X21_1","X21_2","X21_3","X21_4",
		"DENSE","EMPTY","RPT_END","READY"};//,"X20_4","X20_4","X19_4","X19_4"};
	char* return_table[]={"","","","SCLK_IN","SDATA_IN","PS_IN","TEST_IN","SENSOR1","SENSOR2","SENSOR3",
		"LEVEL","WEFT_BRK","X14_4","X15_1","X15_2","X15_3","X15_4","24VJM","PO1_24V","24VWM","FAST",
		"SLOW","FORWD","BACKWD","WARP_BRK"};//,"","","",""};
	strcpy(info,"FPGA PCB test:\n\r");
/* test FPGA*/
	d=0xab;
	outb(p,d);
	DelayMs(100);
	d=inb(p);
	if(d!=0xab)
	{
		strcpy(info,"Error 1: FPGA test failed !");
#ifndef SOFT_RUN
		return ;
#endif
	}
	DisplayInfo("FPGA OK");
/* test FRAM*/
	p=PC_MEM_START_O;
	for(i=0;i<8;i++)
		ram_data[i]=inb(p+i);

	for(i=0;i<8;i++)
	{
		d=((i+1)*30);
		outb(p+i,d);
		DelayMs(1000);
	}
	for(i=0;i<8;i++)
	{
		d=inb(p+i);
		if(d!=((i+1)*30))
		{
			strcpy(info,"FPGA PCB test:\n\rError 2: FRAM test failed !\r\n");
			bOK=0;
		}
	}
	if(bOK==0)
		DisplayInfo(info);
	else
		DisplayInfo("FRAM OK");
	for(i=0;i<8;i++)
	{
		outb(p+i,ram_data[i]);
		DelayMs(1000);
	}
/* test IO of FPGA PCB*/
	for(i=3;i<=24;i++)
	{
		err=OtherTest(i);
		switch(err)
		{
		case OK: break;
		case E01:
			sprintf(info1,"Error %d: %s send 0, %s return 1\r\n",i,send_table[i],return_table[i]);
			strcat(info,info1);
			bOK=0;
			break;
		case E10:
			sprintf(info1,"Error %d: %s send 1, %s return 0\r\n",i,send_table[i],return_table[i]);
			strcat(info,info1);
			bOK=0;
			break;
		case EP:
			sprintf(info1,"Error %d: Unkown error ,send %s  , return %s \r\n",i,send_table[i],return_table[i]);
			strcat(info,info1);
			bOK=0;
		}
		DisplayTest(info1);
	}
	if(bOK)
		strcat(info,"OK, passed!");

	i=strlen(info);
}
void Drv01bPcbTest(char* info)
{
	int i,n;
    ERROR_CODE err;
	char info1[500];
	char* send_table[]={"","","","SCLK_O","SDATA_O","LATCH_O","ENABLE_O"};
	char* return_table[]={"","","","SCLK_IN","SDATA_IN","PS_IN","TEST_IN"};
	BOOL bOK=1;
	strcpy(info,"DRV01B PCB test:\n\r");
	for(i=103;i<=106;i++)
	{
		n=i-100;
		err=OtherTest(i);
		switch(err)
		{
		case OK: break;
		case E01:
			sprintf(info1,"Error %d: %s send 0, %s return 1\r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
			break;
		case E10:
			sprintf(info1,"Error %d: %s send 1, %s return 0\r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
			break;
		case EP:
			sprintf(info1,"Error %d: Unkown error ,send %s  , return %s \r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
		}
	}
	if(bOK)
		strcat(info,"OK, passed!");
}
void MagInterfeaceTest(char* info)
{
	int i,n;
        ERROR_CODE err;
	char info1[500];
	BOOL bOK=1;
	char* send_table[]={"","","","SCLK_O","SDATA_O","LATCH_O","ENABLE_O"};
	char* return_table[]={"","","","SCLK_IN","SDATA_IN","PS_IN","TEST_IN"};
	strcpy(info,"Magnet interface test:\n\r");
	for(i=203;i<=206;i++)
	{
		n=i-200;
		err=OtherTest(i);
		switch(err)
		{
		case OK: break;
		case E01:
			sprintf(info1,"Error %d: %s send 0, %s return 1\r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
			break;
		case E10:
			sprintf(info1,"Error %d: %s send 1, %s return 0\r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
			break;
		case EP:
			sprintf(info1,"Error %d: Unkown error ,send %s  , return %s \r\n",i,send_table[n],return_table[n]);
			strcat(info,info1);
			bOK=0;
		}
	}
	if(bOK)
		strcat(info,"OK, passed!");
}
void Drv01aPcbTest(char* info,BOOL bX19)
{
	int i,n;
        ERROR_CODE err;
	char info1[500];
	BOOL bOK=1;
	char* send_table1[]={"","WEFT 1","WEFT 2","WEFT 3","WEFT 4",
		"WEFT 5","WEFT 6","WEFT 7","WEFT 8","WEFT 9","WEFT 10",
		"WEFT 11","WEFT 12","READY","READY","READY"} ;     //  301-315
	char* send_table2[]={"WEFT 16","DENSE","EMPTY","RPT_END","X19_4","ZONE_A","ZONE_B",
		"JOB_END","X20_4","X21_1","X21_2","X21_3","X21_4"};      //  316-327
	char* return_table[]={"","FAST","SLOW","FORWD","BACKWD","LEVEL",
		"WARP_BRK","WEFT_BRK","X14_4","X15_1","X15_2","X15_3","X15_4",
		"SENSOR1","SENSOR2","SENSOR3"};
	strcpy(info,"DRV01A PCB test:\n\r");
	if(bX19==0)
	{
		for(i=301;i<=315;i++)
		{
			n=i-300;
			err=OtherTest(i);
			switch(err)
			{
			case OK: break;
			case E01:
				sprintf(info1,"Error %d: %s send 0, %s return 1\r\n",i,send_table1[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
				break;
			case E10:
				sprintf(info1,"Error %d: %s send 1, %s return 0\r\n",i,send_table1[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
				break;
			case EP:
				sprintf(info1,"Error %d: Unkown error ,send %s  , return %s \r\n",i,send_table1[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
			}
		}
	}
	else
	{
		for(i=316;i<=327;i++)
		{
			n=i-315;
			err=OtherTest(i);
			switch(err)
			{
			case OK: break;
			case E01:
				sprintf(info1,"Error %d: %s send 0, %s return 1\r\n",i,send_table2[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
				break;
			case E10:
				sprintf(info1,"Error %d: %s send 1, %s return 0\r\n",i,send_table2[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
				break;
			case EP:
				sprintf(info1,"Error %d: Unkown error ,send %s  , return %s \r\n",i,send_table2[n],return_table[n]);
				strcat(info,info1);
				bOK=0;
			}
		}
	}
	if(bOK)
		strcat(info,"OK, passed!");
}

ERROR_CODE OtherTest(int TestNumber)
{
	unsigned short  FPGA_out_port[]={0,0,0,MAP_O,MAP_O,MAP_O,0,MAP_O,MAP_O,MAP_O,
		             SELF_TEST_O,SELF_TEST_O,WEAVER_O,CONTROL_O,CONTROL_O,CONTROL_O,CONTROL_O,
					 SELF_TEST_O,SELF_TEST_O,SELF_TEST_O,SELF_TEST_O,CONTROL_O,CONTROL_O,WEAVER_O,WEAVER_O};
	unsigned short  FPGA_in_port[]={0,0,0,MAP_I,MAP_I,MAP_I,MAP_I,SELF_TEST_1_I,SELF_TEST_1_I,SELF_TEST_1_I,WEAVER_I,
		             WEAVER_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,
					 WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I};
	unsigned short FPGA_out_mask[]={255,255,255,2,4,1,255,2,4,1,1,2,1,1,2,4,8,0x10,0x20,0x40,0x80,0x10,0x20,2,4};
	unsigned short FPGA_in_mask[]={255,255,255,0x40,0x20,8,0x80,1,2,4,0x40,0x10,1,2,4,8,0x10,0x80,0x40,0x20,2,1,4,8,0x20};

	unsigned short  DRV01A_out_port[]={0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223,0x223, /*=CONTROL_O*/
		WEAVER_O,WEAVER_O,WEAVER_O,0x223,0x223,WEAVER_O,SELF_TEST_O,SELF_TEST_O,SELF_TEST_O,WEAVER_O,SELF_TEST_O,SELF_TEST_O,SELF_TEST_O,SELF_TEST_O,SELF_TEST_O};
	unsigned short  DRV01A_in_port[]={0,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,
		SELF_TEST_1_I,SELF_TEST_1_I,SELF_TEST_1_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I};
//	unsigned short DRV01A_out_mask[]={1,2,3,4,5,6,7,8,9,10,11,12,4,4,4,0x10,0x20,2,8,1,2,1,4,0x10,0x20,0x40,0x80};
//	unsigned short DRV01A_in_mask[]={2,1,4,8,0x40,0x20,0x10,1,2,4,8,0x10,1,2,4,2,1,4,8,0x40,0x20,0x10,1,2,4,8,0x10};
	unsigned short DRV01A_out_mask[]={0,1,2,3,4,5,6,7,8,9,10,11,12,4,4,4,0x10,0x20,2,8,1,2,1,4,0x10,0x20,0x40,0x80};
	unsigned short DRV01A_in_mask[]={0,2,1,4,8,0x40,0x20,0x10,1,2,4,8,0x10,1,2,4,2,1,4,8,0x40,0x20,0x10,1,2,4,8,0x10};

	unsigned short  DRV01B_out_port[]={0,0,0,MAP_O,MAP_O,MAP_O,0};
	unsigned short  DRV01B_in_port[]={0,0,0,MAP_I,MAP_I,MAP_I,MAP_I};
	unsigned short DRV01B_out_mask[]={0,0,0,2,4,1,0};
	unsigned short DRV01B_in_mask[]={0,0,0,0x40,0x20,8,0x80};

	unsigned short	p;
	int d;

	if(TestNumber<3)
		return EP;
	if(TestNumber==6 || TestNumber==106 || TestNumber==206)
	{
		p=MAP_O;
		d=0xff;
		outb(p,d);

		p=PC_ENABLE_L_O;
		outb(p,0);
		DelayMs(DELAY_TIME);
		p=MAP_I;
		d=inb(p);
		d=d&0x80;
		if(d!=0)
			return E01;
		p=PC_ENABLE_H_O;
		outb(p,0);
		DelayMs(DELAY_TIME);
		p=MAP_I;
		d=inb(p);
		d=d&0x80;
		if(d==0)
			return E10;
		return OK;
	}
	if(TestNumber<100)     // FPGA PCB
	{
		p=FPGA_out_port[TestNumber];
		if(TestNumber==21 || TestNumber==22)// Dense, Empty: inversed
			d=FPGA_out_mask[TestNumber]; 
		else			
			d=0;
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=FPGA_in_port[TestNumber];
		d=inb(p);
		d=d&FPGA_in_mask[TestNumber];
		if(d!=0)
			return E01;

		p=FPGA_out_port[TestNumber];
		if(TestNumber==21 || TestNumber==22)// Dense, Empty: inversed
			d=0;
		else
			d=FPGA_out_mask[TestNumber];
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=FPGA_in_port[TestNumber];
		d=inb(p);
		d=d&FPGA_in_mask[TestNumber];
		if(d==0)
			return E10;
		return OK;
	}

	if(TestNumber<200)      //DRV01B
	{
		TestNumber-=100;
		p=DRV01B_out_port[TestNumber];
		d=0;
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=DRV01B_in_port[TestNumber];
		d=inb(p);
		d=d&DRV01B_in_mask[TestNumber];
		if(d!=0)
			return E01;

		p=DRV01B_out_port[TestNumber];
		d=DRV01B_out_mask[TestNumber];
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=DRV01B_in_port[TestNumber];
		d=inb(p);
		d=d&DRV01B_in_mask[TestNumber];
		if(d==0)
			return E10;
		return OK;
	}

	if(TestNumber<300)      //Meg_interface
	{
		TestNumber-=200;
		p=DRV01B_out_port[TestNumber];
		d=0;
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=DRV01B_in_port[TestNumber];
		d=inb(p);
		d=d&DRV01B_in_mask[TestNumber];
		if(d==0 && TestNumber==4)
			return E01;
		if(d!=0 && TestNumber!=4)
			return E01;

		p=DRV01B_out_port[TestNumber];
		d=DRV01B_out_mask[TestNumber];
		outb(p,d);
		DelayMs(DELAY_TIME);
		p=DRV01B_in_port[TestNumber];
		d=inb(p);
		d=d&DRV01B_in_mask[TestNumber];
		if(d!=0  && TestNumber==4)
			return E10;
		if(d==0  && TestNumber!=4)
			return E10;
		return OK;
	}
                      //DRV01A测试
	TestNumber-=300;
	p=DRV01A_out_port[TestNumber];
	if(TestNumber<=17)
		d=DRV01A_out_mask[TestNumber];
	else
		d=0;
	outb(p,d);
	DelayMs(DELAY_TIME);
	p=DRV01A_in_port[TestNumber];
	d=inb(p);
	d=d&DRV01A_in_mask[TestNumber];
	if(d!=0)
		return E01;

	p=DRV01A_out_port[TestNumber];
	if(TestNumber<=17)
		d=0;
	else
		d=DRV01A_out_mask[TestNumber];
		outb(p,d);
	DelayMs(DELAY_TIME);
	p=DRV01A_in_port[TestNumber];
	d=inb(p);
	d=d&DRV01A_in_mask[TestNumber];
//	if(TestNumber>15 && d==0)
	if(d==0)
		return E10;
//	if(TestNumber<=15 && d!=0)
//		return E10;
	return OK;
}

void TestInputDT(char* info)
{
	unsigned short  DRV01A_in_port[]={WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,WEAVER_I,
		SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,SELF_TEST_2_I,
		SELF_TEST_1_I,SELF_TEST_1_I,SELF_TEST_1_I,MAP_I};
	unsigned short DRV01A_in_mask[]={2,1,4,8,0x40,0x20,0x10,1,2,4,8,0x10,1,2,4,8};
	unsigned short	p;
	int d;
	int i;
	for(i=0;i<16;i++)
	{
		p=DRV01A_in_port[i];
		d=inb(p);
		d=d&DRV01A_in_mask[i];
		if(d==0)
			info[i]='I';
		else
			info[i]='.';
		DelayMs(DELAY_TIME);

	}
	info[i]='\0';
}

void TestOutDT(char* out_led,char* out_name,int num,BOOL on,CONTROL* control,SELF_TEST__O* selftest,WEAO* weao,MAPO* mapo)
{
	char* name[]={"","WEFT 1","WEFT 2","WEFT 3","WEFT 4",
		"WEFT 5","WEFT 6","WEFT 7","WEFT 8","WEFT 9","WEFT 10",
		"WEFT 11","WEFT 12","WEFT 13","WEFT 14","WEFT 15",
		"WEFT 16","DENSE","EMPTY","RPT_END","X19_4","ZONE_A","ZONE_B",
		"JOB_END","X20_4","X21_1","X21_2","X21_3","X21_4",
		"READY","SCLK_OUT","LAT_OUT","ENA_OUT"};
	unsigned short p,data;
				
	int i;
	for(i=0;i<num;i++)
		out_name[i]=' ';
	sprintf(out_name+num,"%s\n\r",name[num]);
	if(on)
		out_led[num]='I';
	else
		out_led[num]='.';
	out_led[num+1]='\0'; 
	out_led[0]=' ';
	if(num<17)
	{
		if(on)
		{
			out_led[num]='I';
			for(i=1;i<num;i++)
				out_led[num]='.';
		}
		else
			out_led[num]='.';
		p=0x223;    // CONTROL_O
		outb(p,control->_byte);
	}
	else
		switch(num)
		{
		case 17:
			p=0x223;
			control->_bit.k1=1-on;
			outb(p,control->_byte);  //dense
			break;
		case 18:
			p=0x223;
			control->_bit.ls=1-on;
			outb(p,control->_byte);  //empty
			break;
		case 19:
			p=WEAVER_O;
			weao->_bit.rpt_end=1-on;
			outb(p,weao->_byte);  //rpt_end
			break;
		case 20:
			p=SELF_TEST_O;
			selftest->_bit.x19_4=1-on;
			outb(p,selftest->_byte);  //x19_4
			break;
		case 21:
			p=SELF_TEST_O;
			selftest->_bit.zone_a=1-on;
			outb(p,selftest->_byte); //zone_a
			break;
		case 22:
			p=SELF_TEST_O;
			selftest->_bit.zone_b=1-on;
			outb(p,selftest->_byte); //zone_b
			break;
		case 23:
			p=WEAVER_O;
			weao->_bit.job_end;
			outb(p,weao->_byte);  //job_end
			break;
		case 24:
			p=SELF_TEST_O;
			selftest->_bit.x20_4=1-on;
			outb(p,selftest->_byte);  //x20_4
			break;
		case 25:
			p=SELF_TEST_O;
			selftest->_bit.x21_1=1-on;
			outb(p,selftest->_byte);  //x21_1
			break;
		case 26:
			p=SELF_TEST_O;
			selftest->_bit.x21_2=1-on;
			outb(p,selftest->_byte);  //x21_2
			break;
		case 27:
			p=SELF_TEST_O;
			selftest->_bit.x21_3=1-on;
			outb(p,selftest->_byte);  //x21_3
			break;
		case 28:
			p=SELF_TEST_O;
			selftest->_bit.x21_4=1-on;
			outb(p,selftest->_byte);  //x21_4
			break;
		case 29:
			p=WEAVER_O;
			weao->_bit.ready=on;
			outb(p,weao->_byte);  //ready
			break;
		case 30:
			p=MAP_O;
			mapo->_bit.sclk=1-on;
			outb(p,mapo->_byte);  //sclk
			break;
		case 31:
			p=MAP_O;
			mapo->_bit.latch=1-on;
			outb(p,mapo->_byte); //latch
			break;
		case 32:
			p=MAP_O;
			outb(p,0xff);
			if(on)
				p=PC_ENABLE_H_O;
			else
				p=PC_ENABLE_L_O;
			outb(p,0);  //enable
			break;
		}

}