📄 fir3.mdl
字号:
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "fir3"
Location [163, 111, 950, 703]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Chirp Signal"
Ports [0, 1]
Position [25, 50, 55, 80]
SourceBlock "simulink/Sources/Chirp Signal"
SourceType "chirp"
ShowPortLabels on
f1 "0.1"
T "10"
f2 "1"
VectorParams1D on
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [225, 205, 270, 255]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [225, 340, 270, 390]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [225, 460, 270, 510]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
sclr off
SIGNALCOMPILER_PARAMS "depth;1;clken;off;MaskValue;1;sclr;off;"
}
Block {
BlockType Gain
Name "Gain"
Position [125, 50, 155, 80]
Gain "127"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [4, 1]
Position [480, 267, 515, 343]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Parallel \nAdder Sub"
"tractor"
SourceType "Sum AlteraBlockSet"
Inputs "4"
direction "++++"
pipeline on
clken off
MaskValue "1"
SIGNALCOMPILER_PARAMS "clken;off;direction;++++;Inputs;4;MaskValue;1;p"
"ipeline;on;"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [705, 146, 735, 179]
Location [188, 390, 512, 629]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [564, 433, 633, 480]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/SignalCompiler"
SourceType "SignalCompiler"
family "ACEX 1K"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "d:\\my documents\\my designs\\matlab\\fir3"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation on
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "6.1"
}
Block {
BlockType Reference
Name "h0"
Ports [1, 1]
Position [325, 122, 385, 168]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "63"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "63"
SIGNALCOMPILER_PARAMS "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;63;clken;off;MaskValue;1;lpm;off;"
}
Block {
BlockType Reference
Name "h1"
Ports [1, 1]
Position [325, 207, 385, 253]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
SIGNALCOMPILER_PARAMS "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;127;clken;off;MaskValue;1;lpm;off;"
}
Block {
BlockType Reference
Name "h2"
Ports [1, 1]
Position [325, 342, 385, 388]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
SIGNALCOMPILER_PARAMS "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;127;clken;off;MaskValue;1;lpm;off;"
}
Block {
BlockType Reference
Name "h3"
Ports [1, 1]
Position [330, 462, 390, 508]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "63"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "63"
SIGNALCOMPILER_PARAMS "BusType;Signed Integer;bwl;8;bwr;0;pipeline;0;g"
"ain;63;clken;off;MaskValue;1;lpm;off;"
}
Block {
BlockType Reference
Name "xin"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 137, 160, 153]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "xin"
ppat "d:\\my documents\\my designs\\matlab\\fir3\\DSP"
"Builder_fir3"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Input Port;bwl;8;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "yout"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [565, 297, 630, 313]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "yout"
ppat "d:\\my documents\\my designs\\matlab\\fir3\\DSP"
"Builder_fir3"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Output Port;bwl;18;"
"bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Line {
SrcBlock "xin"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "h0"
DstPort 1
}
Branch {
Points [0, 85]
DstBlock "Delay"
DstPort 1
}
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "h1"
DstPort 1
}
Branch {
Points [0, 70; -115, 0; 0, 65]
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
DstBlock "h2"
DstPort 1
}
Branch {
Points [0, 65; -115, 0; 0, 55]
DstBlock "Delay2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
DstBlock "h3"
DstPort 1
}
Line {
SrcBlock "h0"
SrcPort 1
Points [35, 0; 0, 130]
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Line {
SrcBlock "h1"
SrcPort 1
Points [25, 0; 0, 65]
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Line {
SrcBlock "h2"
SrcPort 1
Points [35, 0; 0, -50]
DstBlock "Parallel \nAdder Subtractor"
DstPort 3
}
Line {
SrcBlock "h3"
SrcPort 1
Points [35, 0; 0, -150]
DstBlock "Parallel \nAdder Subtractor"
DstPort 4
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "yout"
DstPort 1
}
Line {
SrcBlock "Chirp Signal"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [35, 0]
Branch {
Points [415, 0; 0, 90]
DstBlock "Scope"
DstPort 1
}
Branch {
Points [0, 40; -115, 0]
DstBlock "xin"
DstPort 1
}
}
Line {
SrcBlock "yout"
SrcPort 1
Points [25, 0; 0, -135]
DstBlock "Scope"
DstPort 2
}
}
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -