os_cpu_a.s

uC/OS-II Notes from Nohau Corporation The code associated with this readme.txt file is provided "as

//
// Arguments   : none
//********************************************************************************************************

OSIntCtxSw:
    bralid r15,OSTaskSwHook            //   Call user task switch hook
    nop

    lwi   r3,r0,OSTCBHighRdy           //   OSTCBCur  = OSTCBHighRdy
    swi   r3,r0,OSTCBCur               //   

    lwi   r4,r0,OSPrioHighRdy          //   OSPrioCur = OSPrioHighRdy
    swi   r4,r0,OSPrioCur              //   

    lwi   r1,r3,0                      //   Load SP into uB
//  POP
    lwi r0,r1,register_dumpin - 0
//  lwi r1,r1,register_dumpin - 4
    lwi r2,r1,register_dumpin - 8
    lwi r3,r1,register_dumpin-12
    lwi r4,r1,register_dumpin-16
    lwi r5,r1,register_dumpin-20
    lwi r6,r1,register_dumpin-24
    lwi r7,r1,register_dumpin-28
    lwi r8,r1,register_dumpin-32
    lwi r9,r1,register_dumpin-36
    lwi r10,r1,register_dumpin-40
    lwi r11,r1,register_dumpin-44
    lwi r12,r1,register_dumpin-48
    lwi r13,r1,register_dumpin-52
    lwi r14,r1,register_dumpin-56
    lwi r15,r1,register_dumpin-60
    lwi r16,r1,register_dumpin-64
    lwi r17,r1,register_dumpin-68
    lwi r18,r1,register_dumpin-72
    lwi r19,r1,register_dumpin-76
    lwi r20,r1,register_dumpin-80
    lwi r21,r1,register_dumpin-84
    lwi r22,r1,register_dumpin-88
    lwi r23,r1,register_dumpin-92
    lwi r24,r1,register_dumpin-96
    lwi r25,r1,register_dumpin-100
    lwi r26,r1,register_dumpin-104
    lwi r27,r1,register_dumpin-108
    lwi r28,r1,register_dumpin-112
    lwi r29,r1,register_dumpin-116
    lwi r30,r1,register_dumpin-120
    lwi r31,r1,register_dumpin-128
    mts rmsr, r31
    lwi r31,r1,register_dumpin-124
//  END POP
    addi r1,r1,0x90                     // Set r1 to Top of stack
    lwi r14,r1,-8                       // Use r14 to link
    rtid r14,0                          // Run task
    nop


//********************************************************************************************************
//                                           SYSTEM TICK ISR
//
// Description : This function is the ISR used to notify uC/OS-II that a system tick has occurred.  You
//               must setup the uBlaze interrupt vector table so that an OUTPUT COMPARE interrupt
//               vectors to this function. (Done in C in Main)
//
// Arguments   : none
//
// Notes       :  1) The 'tick ISR' assumes the we are using 
//
//********************************************************************************************************

OSTickISR:
//  PUSH
    swi r0,r1,register_dump - 0 
    swi r1,r1,register_dump - 4
    swi r2,r1,register_dump - 8
    swi r3,r1,register_dump-12
    swi r4,r1,register_dump-16
    swi r5,r1,register_dump-20
    swi r6,r1,register_dump-24
    swi r7,r1,register_dump-28
    swi r8,r1,register_dump-32
    swi r9,r1,register_dump-36
    swi r10,r1,register_dump-40
    swi r11,r1,register_dump-44
    swi r12,r1,register_dump-48
    swi r13,r1,register_dump-52
    swi r14,r1,register_dump-56
    swi r15,r1,register_dump-60
    swi r16,r1,register_dump-64
    swi r17,r1,register_dump-68
    swi r18,r1,register_dump-72
    swi r19,r1,register_dump-76
    swi r20,r1,register_dump-80
    swi r21,r1,register_dump-84
    swi r22,r1,register_dump-88
    swi r23,r1,register_dump-92
    swi r24,r1,register_dump-96
    swi r25,r1,register_dump-100
    swi r26,r1,register_dump-104
    swi r27,r1,register_dump-108
    swi r28,r1,register_dump-112
    swi r29,r1,register_dump-116
    swi r30,r1,register_dump-120
    swi r31,r1,register_dump-124
    mfs r31, rmsr
    swi r31,r1,register_dump-128
//  PUSH END

    add r3,r0,r14
    swi r3,r1,register_dump+0x04       //Pc
    swi r3,r1,register_dump+0x08       //PC
    add r3,r0,r0
    swi r3,r1,register_dump+0x0C       //Data =0
    

    addi r3,r0,0x90
    sub r1,r1,r3                       // Set r1 to new Top of stack


    lwi    r3,r0,OSIntNesting          //  Notify uC/OS-II about ISR
    addi  r3,r3,0x01000000
    swi    r3,r0,OSIntNesting

//                                     //   if (OSIntNesting == 1) {
    xori    r3,r3,0x01000000           //  
    bnei    r3,OSTickISR1              //   

    lwi  r3,r0,OSTCBCur                //   OSTCBCur->OSTCBStkPtr = Stack Pointer
    swi  r1,r3,0
                                       //  }

OSTickISR1:
//  cli                                //   Enable interrupts to allow interrupt nesting (to do)

    ori r4,r0,0x07fff8300              //  Prep timer for next interrupt
    ori r4,r4,0x080000000
    lwi  r3,r4,0
    swi  r3,r4,0

    bralid r15,OSTimeTick              //  Call uC/OS-II's tick updating function
    nop

    bralid r15,OSIntExit               //  Notify uC/OS-II about end of ISR
    nop

//  POP
    lwi r0,r1,register_dumpin - 0
//  lwi r1,r1,register_dumpin - 4
    lwi r2,r1,register_dumpin - 8
    lwi r3,r1,register_dumpin-12
    lwi r4,r1,register_dumpin-16
    lwi r5,r1,register_dumpin-20
    lwi r6,r1,register_dumpin-24
    lwi r7,r1,register_dumpin-28
    lwi r8,r1,register_dumpin-32
    lwi r9,r1,register_dumpin-36
    lwi r10,r1,register_dumpin-40
    lwi r11,r1,register_dumpin-44
    lwi r12,r1,register_dumpin-48
    lwi r13,r1,register_dumpin-52
    lwi r14,r1,register_dumpin-56
    lwi r15,r1,register_dumpin-60
    lwi r16,r1,register_dumpin-64
    lwi r17,r1,register_dumpin-68
    lwi r18,r1,register_dumpin-72
    lwi r19,r1,register_dumpin-76
    lwi r20,r1,register_dumpin-80
    lwi r21,r1,register_dumpin-84
    lwi r22,r1,register_dumpin-88
    lwi r23,r1,register_dumpin-92
    lwi r24,r1,register_dumpin-96
    lwi r25,r1,register_dumpin-100
    lwi r26,r1,register_dumpin-104
    lwi r27,r1,register_dumpin-108
    lwi r28,r1,register_dumpin-112
    lwi r29,r1,register_dumpin-116
    lwi r30,r1,register_dumpin-120
    lwi r31,r1,register_dumpin-128
    mts rmsr, r31
    lwi r31,r1,register_dumpin-124
//  END POP
    addi r1,r1,0x90                     // Set r1 to Top of stack
    rtid r14,0                          // Run task
    nop

AppTickInitAsm:
    ori r4,r0,0x07fff8300               //Bad but used to get FFFF in to r4H
    ori r4,r4,0x080000000
    addi  r3,r0,0x7a120                 //50000 -> 1mS if 50MHz timer clk
    swi  r3,r4,0x4
    addi r3,r0,0x0120
    swi  r3,r4,0
                                        //0,0,0,0,0,EnAll,Pwm,Int
    addi r3,r0,0x00D2                   //TEn1,IntEn1,NoRes0,ReL1,NoCapI0,Comp0,Down1,Comp0
    swi  r3,r4,0
    rtsd r15,8
    nop

 OS_ENTER_CRITICAL_ASM1:
    swi r31,r1,-4           
    mfs r31, rmsr           /* Disable the Interupts */
    andi r31,r31, 0xfffffffd         
    mts rmsr, r31
    swi r0,r0,IntEn_mem     /* Let our var know that interrupt is off*/  
    lwi r31,r1,-4
    rtsd r15,8
    nop

 OS_EXIT_CRITICAL_ASM1:
    swi r31,r1,-4           
    addi r31,r0,2          /* Show int On for user */
    swi r31,r0,IntEn_mem   /* Let our var know that interrupt is on*/
    mfs r31, rmsr          /* Read the MSR */   
    ori r31,r31,0x2 //0x2        
    mts rmsr, r31          /* Enable the Interupts */
    lwi r31,r1,-4
    rtsd r15,8
    nop
    
/* Disable the Interupts #2 gets stuck, we have no PUSH/POP in MB */
OS_ENTER_CRITICAL_ASM2:         
    brai OS_ENTER_CRITICAL_ASM2 
    brai 8                      /* You could use this jump to exeption*/
                                /* We have no push so use #3          */
                                
/* Enable the Interupts #2 gets stuck, we have no PUSH/POP in MB */                                
OS_EXIT_CRITICAL_ASM2:         
    brai OS_EXIT_CRITICAL_ASM2  
    brai 8                      /* You could use this jump to exeption*/
                                /* We have no pop so use #3           */
                                                                
OS_ENTER_CRITICAL_ASM3:
    mfs r3, rmsr            /* read cpu int_en                        */
    andi r4,r3, 0xfffffffd  /* Compiler uses r3 for return of cpu_sr  */     
    mts rmsr,r4             /* r3/r4 is used for return val,int off   */
    lwi r4,r0,IntEn_mem     /* or in our own bit,we could be comming from interrupt*/
    ori r4,r4,2             /* Nedded to not turn off (see readme)    */
    or r3,r3,r4            
    swi r0,r0,IntEn_mem     /* Show int off next time                 */
    rtsd r15,8
    nop

OS_EXIT_CRITICAL_ASM3:
    add r18,r0,r5           /* r18 used as it is for asm..         */
    andi r18,r18,2          /* Show int On/Off as r5 for next time */
    swi r18,r0,IntEn_mem    /* Let our var know that interrupt is on/off */
    mts rmsr,r5             /* Restore the Interupts               */
    rtsd r15,8              /* Compiler uses r5 for param cpu_sr   */
    nop


    /* Temporary memory needed for the interrupt mem  */
    .data
    .align 4
IntEn_mem:
    .int 0

//  /* 1 words containing a 0 (not used included to show syntax)*/
//  .align 2
//temp_mem_fill:
//  .fill 1, 4, 0

.end    os_cpu_a_s