os_cpu.h

uC/OS-II Notes from Nohau Corporation The code associated with this readme.txt file is provided "as

/*
*********************************************************************************************************
*                                               uC/OS-II
*                                         The Real-Time Kernel
*
*                         (c) Copyright 2002, Jean J. Labrosse, Weston, FL
*                                          All Rights Reserved
*
*                                       Revised by Jorgen Andersson for
*                                          uBlaze Specific code
*                                            (Xilinx C V2.2)
*
* File         : OS_CPU.H
* By           : Jean J. Labrosse
* Revised      : Jorgen Andersson, Nohau Corporation (10/30/02)
* Port Version : V1.00 (for uC/OS-II V2.51 and higher)
*********************************************************************************************************
*/

/*
*********************************************************************************************************
*                                              DATA TYPES
*********************************************************************************************************
*/

typedef unsigned char  BOOLEAN;
typedef unsigned char  INT8U;                    /* Unsigned  8 bit quantity                           */
typedef signed   char  INT8S;                    /* Signed    8 bit quantity                           */
typedef unsigned short INT16U;                   /* Unsigned 16 bit quantity                           */
typedef signed   short INT16S;                   /* Signed   16 bit quantity                           */
typedef unsigned long  INT32U;                   /* Unsigned 32 bit quantity                           */
typedef signed   long  INT32S;                   /* Signed   32 bit quantity                           */
typedef float          FP32;                     /* Single precision floating point                    */
typedef double         FP64;                     /* Double precision floating point                    */

#define BYTE           INT8S                     /* Define data types for backward compatibility ...   */
#define UBYTE          INT8U                     /* ... to uC/OS V1.xx                                 */
#define WORD           INT16S
#define UWORD          INT16U
#define LONG           INT32S
#define ULONG          INT32U

typedef unsigned long  OS_STK;                   /* Each stack entry is 8-bit wide                     */
typedef unsigned long  OS_CPU_SR;                /* Define size of CPU status register (PSW = 32 bits) */

/*
*********************************************************************************************************
*                                              CONSTANTS
*********************************************************************************************************
*/

#ifndef  FALSE
#define  FALSE    0
#endif

#ifndef  TRUE
#define  TRUE     1
#endif

/* 
*********************************************************************************************************
*                                           Motorola uBlaze
*
* Method #1:  Disable/Enable interrupts using simple instructions.  After critical section, interrupts
*             will be enabled even if they were disabled before entering the critical section.
*
* Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In other words, if 
*             interrupts were disabled before entering the critical section, they will be disabled when
*             leaving the critical section.
*
* Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
*             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
*             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
*             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
*             into the CPU's status register.
*
* NOTE(s)  :  1) The current version of the compiler does NOT allow method #2 to be used without changing
*                the processor independent portion of uC/OS-II.
*********************************************************************************************************
*/


#define  OS_CRITICAL_METHOD    3

#if      OS_CRITICAL_METHOD == 1
#define  OS_ENTER_CRITICAL()  OS_ENTER_CRITICAL_ASM1() 
#define  OS_EXIT_CRITICAL()   OS_EXIT_CRITICAL_ASM1()
#endif

#if      OS_CRITICAL_METHOD == 2
#define  OS_ENTER_CRITICAL()  OS_ENTER_CRITICAL_ASM2();  
#define  OS_EXIT_CRITICAL()   OS_EXIT_CRITICAL_ASM2();
#endif

#if      OS_CRITICAL_METHOD == 3
#define  OS_ENTER_CRITICAL()  cpu_sr = OS_ENTER_CRITICAL_ASM3()
#define  OS_EXIT_CRITICAL()   OS_EXIT_CRITICAL_ASM3(cpu_sr)
#endif



#define  OS_TASK_SW()         OSCtxSw() 

#define  OS_STK_GROWTH        1                  /* Define stack growth: 1 = Down, 0 = Up              */

#define  CPU_INT_EN()         OS_EXIT_CRITICAL_ASM1(); 
#define  CPU_INT_DIS()        OS_ENTER_CRITICAL_ASM1();