📄 ep93xx.h
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// RASTER#define RASTER_BASE (REGS_BASE + 0x00030000)#define VLINESTOTAL (RASTER_BASE + 0x0000)#define VSYNCSTRTSTOP (RASTER_BASE + 0x0004)#define VACTIVESTRTSTOP (RASTER_BASE + 0x0008)#define VCLKSTRTSTOP (RASTER_BASE + 0x000C)#define HCLKSTOTAL (RASTER_BASE + 0x0010)#define HSYNCSTRTSTOP (RASTER_BASE + 0x0014)#define HACTIVESTRTSTOP (RASTER_BASE + 0x0018)#define HCLKSTRTSTOP (RASTER_BASE + 0x001C)#define BRIGHTNESS (RASTER_BASE + 0x0020)#define VIDEOATTRIBS (RASTER_BASE + 0x0024)#define VIDSCRNPAGE (RASTER_BASE + 0x0028)#define VIDSCRNHPG (RASTER_BASE + 0x002C)#define SCRNLINES (RASTER_BASE + 0x0030)#define LINELENGTH (RASTER_BASE + 0x0034)#define VLINESTEP (RASTER_BASE + 0x0038)#define LINECARRY (RASTER_BASE + 0x003C)#define BLINKRATE (RASTER_BASE + 0x0040)#define BLINKMASK (RASTER_BASE + 0x0044)#define BLINKPATRN (RASTER_BASE + 0x0048)#define PATTRNMASK (RASTER_BASE + 0x004C)#define BKGRNDOFFSET (RASTER_BASE + 0x0050)#define PIXELMODE (RASTER_BASE + 0x0054)#define PARLLIFOUT (RASTER_BASE + 0x0058)#define PARLLIFIN (RASTER_BASE + 0x005C)#define CURSORADRSTART (RASTER_BASE + 0x0060)#define CURSORADRRESET (RASTER_BASE + 0x0064)#define CURSORSIZE (RASTER_BASE + 0x0068)#define CURSORCOLOR1 (RASTER_BASE + 0x006C)#define CURSORCOLOR2 (RASTER_BASE + 0x0070)#define CURSORXYLOC (RASTER_BASE + 0x0074)#define CURSORDSCANLHYLOC (RASTER_BASE + 0x0078)#define RASTERSWLOCK (RASTER_BASE + 0x007C)#define GRYSCLLUTR (RASTER_BASE + 0x0080)#define VIDSIGRSLTVAL (RASTER_BASE + 0x0200)#define VIDSIGCTL (RASTER_BASE + 0x0204)#define VSIGSTRTSTOP (RASTER_BASE + 0x0208)#define HSIGSTRTSTOP (RASTER_BASE + 0x020C)#define SIGCLRSTR (RASTER_BASE + 0x0210)#define ACRATE (RASTER_BASE + 0x0214)#define LUTSWCTRL (RASTER_BASE + 0x0218)#define CURSORBLINKCOLOR1 (RASTER_BASE + 0x021C)#define CURSORBLINKCOLOR2 (RASTER_BASE + 0x0220)#define CURSORBLINKRATECTRL (RASTER_BASE + 0x0224)#define VBLANKSTRTSTOP (RASTER_BASE + 0x0228)#define HBLANKSTRTSTOP (RASTER_BASE + 0x022C)#define EOLOFFSET (RASTER_BASE + 0x0230)#define FIFOLEVEL (RASTER_BASE + 0x0234)#define GRYSCLLUTG (RASTER_BASE + 0x0280)#define GRYSCLLUTB (RASTER_BASE + 0x0300)#define COLORLUT (RASTER_BASE + 0x0400)// SDRAM#define SDRAM_BASE (REGS_BASE + 0x00060000)#define GLCONFIG (SDRAM_BASE + 0x0004)#define REFRSHTIMR (SDRAM_BASE + 0x0008)#define BOOTSTS (SDRAM_BASE + 0x000C)#define SDRAMDEVCFG0 (SDRAM_BASE + 0x0010)#define SDRAMDEVCFG1 (SDRAM_BASE + 0x0014)#define SDRAMDEVCFG2 (SDRAM_BASE + 0x0018)#define SDRAMDEVCFG3 (SDRAM_BASE + 0x001C)// SMC#define SMC_BASE (REGS_BASE + 0x00080000)#define SMCBCR0 (SMC_BASE + 0x0000)#define SMCBCR1 (SMC_BASE + 0x0004)#define SMCBCR2 (SMC_BASE + 0x0008)#define SMCBCR3 (SMC_BASE + 0x000C)#define SMCBCR6 (SMC_BASE + 0x0018)#define SMCBCR7 (SMC_BASE + 0x001C)#define PC1ATTRIBUTE (SMC_BASE + 0x0020)#define PC1COMMON (SMC_BASE + 0x0024)#define PC1IO (SMC_BASE + 0x0028)#define PC2ATTRIBUTE (SMC_BASE + 0x0030)#define PC2COMMON (SMC_BASE + 0x0034)#define PC2IO (SMC_BASE + 0x0038)#define PCMCIACTRL (SMC_BASE + 0x0040)// Boot ROM#define BOOTROM_BASE (BOOTROM_BASE + 0x00090000)// IDE#define IDE_BASE (REGS_BASE + 0x000A0000)#define IDECTRL (IDE_BASE + 0x0000)#define IDECFG (IDE_BASE + 0x0004)#define IDEMDMAOP (IDE_BASE + 0x0008)#define IDEUDMAOP (IDE_BASE + 0x000C)#define IDEDATAOUT (IDE_BASE + 0x0010)#define IDEDATAIN (IDE_BASE + 0x0014)#define IDEMDMADATAOUT (IDE_BASE + 0x0018)#define IDEMDMADATAIN (IDE_BASE + 0x001C)#define IDEUDMADATAOUT (IDE_BASE + 0x0020)#define IDEUDMADATAIN (IDE_BASE + 0x0024)#define IDEUDMASTS (IDE_BASE + 0x0028)#define IDEUDMADEBUG (IDE_BASE + 0x002C)#define IDEUDMAWRBUFSTS (IDE_BASE + 0x0030)#define IDEUDMARDBUFSTS (IDE_BASE + 0x0034)// VIC1#define VIC1_BASE (REGS_BASE + 0x000B0000)#define VIC1IRQSTATUS (VIC1_BASE + 0x0000)#define VIC1FIQSTATUS (VIC1_BASE + 0x0004)#define VIC1RAWINTR (VIC1_BASE + 0x0008)#define VIC1INTSELECT (VIC1_BASE + 0x000C)#define VIC1INTENABLE (VIC1_BASE + 0x0010)#define VIC1INTCLEAR (VIC1_BASE + 0x0014)#define VIC1SOFTINT (VIC1_BASE + 0x0018)#define VIC1SOFTINTCLEAR (VIC1_BASE + 0x001C)#define VIC1PROTECTION (VIC1_BASE + 0x0020)#define VIC1VECTADDR (VIC1_BASE + 0x0030)#define VIC1DEFVECTADDR (VIC1_BASE + 0x0034)#define VIC1VECTADDR0 (VIC1_BASE + 0x0100)#define VIC1VECTADDR1 (VIC1_BASE + 0x0104)#define VIC1VECTADDR2 (VIC1_BASE + 0x0108)#define VIC1VECTADDR3 (VIC1_BASE + 0x010C)#define VIC1VECTADDR4 (VIC1_BASE + 0x0110)#define VIC1VECTADDR5 (VIC1_BASE + 0x0114)#define VIC1VECTADDR6 (VIC1_BASE + 0x0118)#define VIC1VECTADDR7 (VIC1_BASE + 0x011C)#define VIC1VECTADDR8 (VIC1_BASE + 0x0120)#define VIC1VECTADDR9 (VIC1_BASE + 0x0124)#define VIC1VECTADDR10 (VIC1_BASE + 0x0128)#define VIC1VECTADDR11 (VIC1_BASE + 0x012C)#define VIC1VECTADDR12 (VIC1_BASE + 0x0130)#define VIC1VECTADDR13 (VIC1_BASE + 0x0134)#define VIC1VECTADDR14 (VIC1_BASE + 0x0138)#define VIC1VECTADDR15 (VIC1_BASE + 0x013C)#define VIC1VECTCNTL0 (VIC1_BASE + 0x0200)#define VIC1VECTCNTL1 (VIC1_BASE + 0x0204)#define VIC1VECTCNTL2 (VIC1_BASE + 0x0208)#define VIC1VECTCNTL3 (VIC1_BASE + 0x020C)#define VIC1VECTCNTL4 (VIC1_BASE + 0x0210)#define VIC1VECTCNTL5 (VIC1_BASE + 0x0214)#define VIC1VECTCNTL6 (VIC1_BASE + 0x0218)#define VIC1VECTCNTL7 (VIC1_BASE + 0x021C)#define VIC1VECTCNTL8 (VIC1_BASE + 0x0220)#define VIC1VECTCNTL9 (VIC1_BASE + 0x0224)#define VIC1VECTCNTL10 (VIC1_BASE + 0x0228)#define VIC1VECTCNTL11 (VIC1_BASE + 0x022C)#define VIC1VECTCNTL12 (VIC1_BASE + 0x0230)#define VIC1VECTCNTL13 (VIC1_BASE + 0x0234)#define VIC1VECTCNTL14 (VIC1_BASE + 0x0238)#define VIC1VECTCNTL15 (VIC1_BASE + 0x023C)#define VIC1PERIPHID0 (VIC1_BASE + 0x0FE0)#define VIC1PERIPHID1 (VIC1_BASE + 0x0FE4)#define VIC1PERIPHID2 (VIC1_BASE + 0x0FE8)#define VIC1PERIPHID3 (VIC1_BASE + 0x0FEC)// VIC2#define VIC2_BASE (REGS_BASE + 0x000C0000)#define VIC2IRQSTATUS (VIC2_BASE + 0x0000)#define VIC2FIQSTATUS (VIC2_BASE + 0x0004)#define VIC2RAWINTR (VIC2_BASE + 0x0008)#define VIC2INTSELECT (VIC2_BASE + 0x000C)#define VIC2INTENABLE (VIC2_BASE + 0x0010)#define VIC2INTCLEAR (VIC2_BASE + 0x0014)#define VIC2SOFTINT (VIC2_BASE + 0x0018)#define VIC2SOFTINTCLEAR (VIC2_BASE + 0x001C)#define VIC2PROTECTION (VIC2_BASE + 0x0020)#define VIC2VECTADDR (VIC2_BASE + 0x0030)#define VIC2DEFVECTADDR (VIC2_BASE + 0x0034)#define VIC2VECTADDR0 (VIC2_BASE + 0x0100)#define VIC2VECTADDR1 (VIC2_BASE + 0x0104)#define VIC2VECTADDR2 (VIC2_BASE + 0x0108)#define VIC2VECTADDR3 (VIC2_BASE + 0x010C)#define VIC2VECTADDR4 (VIC2_BASE + 0x0110)#define VIC2VECTADDR5 (VIC2_BASE + 0x0114)#define VIC2VECTADDR6 (VIC2_BASE + 0x0118)#define VIC2VECTADDR7 (VIC2_BASE + 0x011C)#define VIC2VECTADDR8 (VIC2_BASE + 0x0120)#define VIC2VECTADDR9 (VIC2_BASE + 0x0124)#define VIC2VECTADDR10 (VIC2_BASE + 0x0128)#define VIC2VECTADDR11 (VIC2_BASE + 0x012C)#define VIC2VECTADDR12 (VIC2_BASE + 0x0130)#define VIC2VECTADDR13 (VIC2_BASE + 0x0134)#define VIC2VECTADDR14 (VIC2_BASE + 0x0138)#define VIC2VECTADDR15 (VIC2_BASE + 0x013C)#define VIC2VECTCNTL0 (VIC2_BASE + 0x0200)#define VIC2VECTCNTL1 (VIC2_BASE + 0x0204)#define VIC2VECTCNTL2 (VIC2_BASE + 0x0208)#define VIC2VECTCNTL3 (VIC2_BASE + 0x020C)#define VIC2VECTCNTL4 (VIC2_BASE + 0x0210)#define VIC2VECTCNTL5 (VIC2_BASE + 0x0214)#define VIC2VECTCNTL6 (VIC2_BASE + 0x0218)#define VIC2VECTCNTL7 (VIC2_BASE + 0x021C)#define VIC2VECTCNTL8 (VIC2_BASE + 0x0220)#define VIC2VECTCNTL9 (VIC2_BASE + 0x0224)#define VIC2VECTCNTL10 (VIC2_BASE + 0x0228)#define VIC2VECTCNTL11 (VIC2_BASE + 0x022C)#define VIC2VECTCNTL12 (VIC2_BASE + 0x0230)#define VIC2VECTCNTL13 (VIC2_BASE + 0x0234)#define VIC2VECTCNTL14 (VIC2_BASE + 0x0238)#define VIC2VECTCNTL15 (VIC2_BASE + 0x023C)#define VIC2PERIPHID0 (VIC2_BASE + 0x0FE0)#define VIC2PERIPHID1 (VIC2_BASE + 0x0FE4)#define VIC2PERIPHID2 (VIC2_BASE + 0x0FE8)#define VIC2PERIPHID3 (VIC2_BASE + 0x0FEC)// TIMER#define TIM_BASE (REGS_BASE + 0x00810000)#define TIMER1LOAD (TIM_BASE + 0x0000)#define TIMER1VALUE (TIM_BASE + 0x0004)#define TIMER1CONTROL (TIM_BASE + 0x0008)#define TIMER1CLEAR (TIM_BASE + 0x000C)#define TIMER2LOAD (TIM_BASE + 0x0020)#define TIMER2VALUE (TIM_BASE + 0x0024)#define TIMER2CONTROL (TIM_BASE + 0x0028)#define TIMER2CLEAR (TIM_BASE + 0x002C)#define TIM_DEBUGVALUELOW (TIM_BASE + 0x0060)#define TIM_DEBUGVALUEHIGH (TIM_BASE + 0x0064)#define TIMER3LOAD (TIM_BASE + 0x0080)#define TIMER3VALUE (TIM_BASE + 0x0084)#define TIMER3CONTROL (TIM_BASE + 0x0088)#define TIMER3CLEAR (TIM_BASE + 0x008C)// TIMER CONTROL regsister bits#define TIMERCONTROL_CLKSEL 0x00000008#define TIMERCONTROL_MODE 0x00000040#define TIMERCONTROL_ENABLE 0x00000080// I2S#define I2S_BASE (REGS_BASE + 0x00820000)#define I2STXCLKCFG (I2S_BASE + 0x0000)#define I2SRXCLKCFG (I2S_BASE + 0x0004)#define I2SCSR (I2S_BASE + 0x0008)#define I2SGCR (I2S_BASE + 0x000c)#define I2STX0LEFT (I2S_BASE + 0x0010)#define I2STX0RIGHT (I2S_BASE + 0x0014)#define I2STX1LEFT (I2S_BASE + 0x0018)#define I2STX1RIGHT (I2S_BASE + 0x001c)#define I2STX2LEFT (I2S_BASE + 0x0020)#define I2STX2RIGHT (I2S_BASE + 0x0024)#define I2STXLCR (I2S_BASE + 0x0028)#define I2STXCR (I2S_BASE + 0x002C)#define I2STXWL (I2S_BASE + 0x0030)#define I2STX0EN (I2S_BASE + 0x0034)#define I2STX1EN (I2S_BASE + 0x0038)#define I2STX2EN (I2S_BASE + 0x003C)#define I2SRX0LEFT (I2S_BASE + 0x0040)#define I2SRX0RIGHT (I2S_BASE + 0x0044)#define I2SRX1LEFT (I2S_BASE + 0x0048)#define I2SRX1RIGHT (I2S_BASE + 0x004c)#define I2SRX2LEFT (I2S_BASE + 0x0050)#define I2SRX2RIGHT (I2S_BASE + 0x0054)#define I2SRXLCR (I2S_BASE + 0x0058)#define I2SRXCR (I2S_BASE + 0x005C)#define I2SRXWL (I2S_BASE + 0x0060)#define I2SRX0EN (I2S_BASE + 0x0064)#define I2SRX1EN (I2S_BASE + 0x0068)#define I2SRX2EN (I2S_BASE + 0x006C)// SECURITY#define SECURITY_BASE (REGS_BASE + 0x00830000)#define EXTENSIONID (SECURITY_BASE + 0x2714)// GPIO#define GPIO_BASE (REGS_BASE + 0x00840000)#define PADR (GPIO_BASE + 0x0000)#define PBDR (GPIO_BASE + 0x0004)#define PCDR (GPIO_BASE + 0x0008)#define PDDR (GPIO_BASE + 0x000C)#define PADDR (GPIO_BASE + 0x0010)#define PBDDR (GPIO_BASE + 0x0014)#define PCDDR (GPIO_BASE + 0x0018)#define PDDDR (GPIO_BASE + 0x001C)#define PEDR (GPIO_BASE + 0x0020)#define PEDDR (GPIO_BASE + 0x0024)#define PFDR (GPIO_BASE + 0x0030)#define PFDDR (GPIO_BASE + 0x0034)#define PGDR (GPIO_BASE + 0x0038)#define PGDDR (GPIO_BASE + 0x003C)#define PHDR (GPIO_BASE + 0x0040)#define PHDDR (GPIO_BASE + 0x0044)#define GPIOFINTTYPE1 (GPIO_BASE + 0x004C)#define GPIOFINTTYPE2 (GPIO_BASE + 0x0050)#define GPIOFEOI (GPIO_BASE + 0x0054)#define GPIOINTENF (GPIO_BASE + 0x0058)#define INTSTATUSF (GPIO_BASE + 0x005c)#define RAWINTSTATUSF (GPIO_BASE + 0x0060)#define GPIOFDB (GPIO_BASE + 0x0064)#define GPIOAINTTYPE1 (GPIO_BASE + 0x0090)#define GPIOAINTTYPE2 (GPIO_BASE + 0x0094)#define GPIOAEOI (GPIO_BASE + 0x0098)#define GPIOAINTEN (GPIO_BASE + 0x009C)⌨️ 快捷键说明
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