chengfaqi.txt

来自「数字系统设计这是有关的相关源代码」· 文本 代码 · 共 67 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY chengfaqi IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END chengfaqi;


ARCHITECTURE SYN OF chengfaqi IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);



	COMPONENT lpm_mult
	GENERIC (
		LPM_WIDTHA		: NATURAL;
		LPM_WIDTHB		: NATURAL;
		LPM_WIDTHP		: NATURAL;
		LPM_WIDTHS		: NATURAL;
		INPUT_B_IS_CONSTANT		: STRING;
		LPM_REPRESENTATION		: STRING;
		USE_EAB		: STRING;
		LPM_PIPELINE		: NATURAL
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			clock	: IN STD_LOGIC ;
			result	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	result    <= sub_wire0(15 DOWNTO 0);

	lpm_mult_component : lpm_mult
	GENERIC MAP (
		LPM_WIDTHA => 8,
		LPM_WIDTHB => 8,
		LPM_WIDTHP => 16,
		LPM_WIDTHS => 16,
		INPUT_B_IS_CONSTANT => "NO",
		LPM_REPRESENTATION => "SIGNED",
		USE_EAB => "OFF",
		LPM_PIPELINE => 1
	)
	PORT MAP (
		dataa => dataa,
		datab => datab,
		clock => clock,
		result => sub_wire0
	);



END SYN;