📄 target.h
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#pragma ADDRESS ad0_addr 03c0H /* A/D register 0 */
#pragma ADDRESS ad1_addr 03c2H /* A/D register 1 */
#pragma ADDRESS ad2_addr 03c4H /* A/D register 2 */
#pragma ADDRESS ad3_addr 03c6H /* A/D register 3 */
#pragma ADDRESS ad4_addr 03c8H /* A/D register 4 */
#pragma ADDRESS ad5_addr 03caH /* A/D register 5 */
#pragma ADDRESS ad6_addr 03ccH /* A/D register 6 */
#pragma ADDRESS ad7_addr 03ceH /* A/D register 7 */
#pragma ADDRESS adcon2_addr 03d4H /* A/D control register 2 */
#pragma ADDRESS adcon0_addr 03d6H /* A/D control register 0 */
#pragma ADDRESS adcon1_addr 03d7H /* A/D control register 1 */
#pragma ADDRESS da0_addr 03d8H /* D/A register 0 */
#pragma ADDRESS da1_addr 03daH /* D/A register 1 */
#pragma ADDRESS dacon_addr 03dcH /* D/A control register */
#pragma ADDRESS p0_addr 03e0H /* Port P0 register */
#pragma ADDRESS p1_addr 03e1H /* Port P1 register */
#pragma ADDRESS pd0_addr 03e2H /* Port P0 direction register */
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
#pragma ADDRESS p2_addr 03e4H /* Port P2 register */
#pragma ADDRESS p3_addr 03e5H /* Port P3 register */
#pragma ADDRESS pd2_addr 03e6H /* Port P2 direction register */
#pragma ADDRESS pd3_addr 03e7H /* Port P3 direction register */
#pragma ADDRESS p4_addr 03e8H /* Port P4 register */
#pragma ADDRESS p5_addr 03e9H /* Port P5 register */
#pragma ADDRESS pd4_addr 03eaH /* Port P4 direction register */
#pragma ADDRESS pd5_addr 03ebH /* Port P5 direction register */
#pragma ADDRESS p6_addr 03ecH /* Port P6 register */
#pragma ADDRESS p7_addr 03edH /* Port P7 register */
#pragma ADDRESS pd6_addr 03eeH /* Port P6 direction register */
#pragma ADDRESS pd7_addr 03efH /* Port P7 direction register */
#pragma ADDRESS p8_addr 03f0H /* Port P8 register */
#pragma ADDRESS p9_addr 03f1H /* Port P9 register */
#pragma ADDRESS pd8_addr 03f2H /* Port P8 direction register */
#pragma ADDRESS pd9_addr 03f3H /* Port P9 direction register */
#pragma ADDRESS p10_addr 03f4H /* Port P10 register */
#pragma ADDRESS pd10_addr 03f6H /* Port P10 direction register */
#pragma ADDRESS pur0_addr 03fcH /* Pull-up control register 0 */
#pragma ADDRESS pur1_addr 03fdH /* Pull-up control register 1 */
#pragma ADDRESS pur2_addr 03feH /* Pull-up control register 2 */
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
/********************************************************
* declare SFR char *
********************************************************/
unsigned char da0_addr; /* D/A register 0 */
#define da0 da0_addr
unsigned char da1_addr; /* D/A register 1 */
#define da1 da1_addr
/*--------------------------------------------------------
Up/down flag ; Use "MOV" instruction when writing to this register.
--------------------------------------------------------*/
unsigned char udf_addr; /* UP/down flag */
#define udf udf_addr
/********************************************************
* declare SFR short *
********************************************************/
/*--------------------------------------------------------
Timer registers : Read and write data in 16-bit units.
--------------------------------------------------------*/
unsigned short ta11_addr; /* Timer A1-1 register */
#define ta11 ta11_addr
unsigned short ta21_addr; /* Timer A2-1 register */
#define ta21 ta21_addr
unsigned short ta41_addr; /* Timer A4-1 register */
#define ta41 ta41_addr
unsigned short tb3_addr; /* Timer B3 register */
#define tb3 tb3_addr
unsigned short tb4_addr; /* Timer B4 register */
#define tb4 tb4_addr
unsigned short tb5_addr; /* Timer B5 register */
#define tb5 tb5_addr
unsigned short ta0_addr; /* Timer A0 register */
#define ta0 ta0_addr
unsigned short ta1_addr; /* Timer A1 register */
#define ta1 ta1_addr
unsigned short ta2_addr; /* Timer A2 register */
#define ta2 ta2_addr
unsigned short ta3_addr; /* Timer A3 register */
#define ta3 ta3_addr
unsigned short ta4_addr; /* Timer A4 register */
#define ta4 ta4_addr
unsigned short tb0_addr; /* Timer B0 register */
#define tb0 tb0_addr
unsigned short tb1_addr; /* Timer B1 register */
#define tb1 tb1_addr
unsigned short tb2_addr; /* Timer B2 register */
#define tb2 tb2_addr
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
#define pm06 pm0_addr.bit.b6 /* Port P40 to P43 function select bit */
#define pm07 pm0_addr.bit.b7 /* BCLK output disable bit */
/*------------------------------------------------------
Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm13 pm1_addr.bit.b3 /* Intermal reserved area expansion bit */
/* #define pm14 pm1_addr.bit.b4 */ /* Memory area expansion bit */
/* #define pm15 pm1_addr.bit.b5 */ /* Memory area expansion bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit 1 */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit 1 */
/*------------------------------------------------------
Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define csr csr_addr.byte
#define cs0 csr_addr.bit.b0 /* CS0~ output enable bit */
#define cs1 csr_addr.bit.b1 /* CS1~ output enable bit */
#define cs2 csr_addr.bit.b2 /* CS2~ output enable bit */
#define cs3 csr_addr.bit.b3 /* CS3~ output enable bit */
#define cs0w csr_addr.bit.b4 /* CS0~ wait bit */
#define cs1w csr_addr.bit.b5 /* CS1~ wait bit */
#define cs2w csr_addr.bit.b6 /* CS2~ wait bit */
#define cs3w csr_addr.bit.b7 /* CS3~ wait bit */
/*------------------------------------------------------
Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control registers 0 and 1 */
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode registers 0 and 1 */
#define prc2 prcr_addr.bit.b2 /* Enables writing to port P9 direction register and SI/Oi control register(i=3,4) */
/*------------------------------------------------------
Data bank register
------------------------------------------------------*/
/* union byte_def dbr_addr; */
/* #define dbr dbr_addr.byte */
/* #define ofs dbr_addr.bit.b2 */ /* Offset bit */
/* #define bsr0 dbr_addr.bit.b3 */ /* Bank select bit 0 */
/* #define bsr1 dbr_addr.bit.b4 */ /* Bank select bit 1 */
/* #define bsr2 dbr_addr.bit.b5 */ /* Bank select bit 2 */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
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