seg.vhd

来自「last time when i came here to find some 」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;

entity seg_dec is
  
  port (
    cin  : in  std_logic_vector(3 downto 0);
    cout : out std_logic_vector(6 downto 0));
end seg_dec;

architecture rtl of seg_dec is
begin
  process(cin)
  begin
    case cin is
      when "0000" => cout <= "1000000";
      when "0001" => cout <= "1111001";
      when "0010" => cout <= "0100100";
      when "0011" => cout <= "0110000";
                     when"0100" => cout <= "0011001";
      when "0101" => cout <= "0010010";
                     when"0110" => cout <= "0000010";
                     when"0111" => cout <= "1111000";
                     when"1000" => cout <= "0000000";
                     when"1001" => cout <= "0010000";
      when others => cout <= "1000000";
    end case;
  end process;
end rtl;