📄 top_test.vhd
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tb_counter_4bit isend tb_counter_4bit;architecture tb of tb_counter_4bit is component counter_4bit port ( reset : in std_logic; clk : in std_logic; power : in std_logic; start : in std_logic; stop : in std_logic; setmin : in std_logic; sethour : in std_logic; cout_seg : out std_logic_vector(6 downto 0); cout_seg_10s : out std_logic_vector(6 downto 0); cout_seg_1m : out std_logic_vector(6 downto 0); cout_seg_10m : out std_logic_vector(6 downto 0); cout_seg_1h : out std_logic_vector(6 downto 0); cout_seg_10h : out std_logic_vector(6 downto 0)); end component; -- component seg_dec -- port ( -- cin : in std_logic_vector(3 downto 0); -- cout : out std_logic_vector(6 downto 0));-- end component; signal tb_reset : std_logic := '1'; signal clk : std_logic := '0'; signal tb_power : std_logic; signal tb_start : std_logic; signal tb_stop : std_logic; signal tb_setmin : std_logic; signal tb_sethour : std_logic; signal tb_cout_seg_1s : std_logic_vector(6 downto 0) := "0000000"; signal tb_cout_seg_10s : std_logic_vector(6 downto 0) := "0000000"; signal tb_cout_seg_1m : std_logic_vector(6 downto 0) := "0000000"; signal tb_cout_seg_10m : std_logic_vector(6 downto 0) := "0000000"; signal tb_cout_seg_1h : std_logic_vector(6 downto 0) := "0000000"; signal tb_cout_seg_10h : std_logic_vector(6 downto 0) := "0000000"; begin u10 : counter_4bit port map ( reset => tb_reset, clk => clk, power =>tb_power, start => tb_start, stop => tb_stop, setmin =>tb_setmin, sethour =>tb_sethour, cout_seg => tb_cout_seg_1s, cout_seg_10s => tb_cout_seg_10s, cout_seg_1m => tb_cout_seg_1m, cout_seg_10m => tb_cout_seg_10m, cout_seg_1h => tb_cout_seg_1h, cout_seg_10h => tb_cout_seg_10h); tb_reset <= '0' after 100 ns; tb_start <='1' after 200 ns; tb_stop <='0' after 200 ns; clk <= not clk after 50 ns; end tb;
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