counter.vhd

last time when i came here to find some clock references. but most of them can not works well. so th

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity counter_4bit is
  port (
    reset        : in  std_logic;
    clk          : in  std_logic;
    power        : in  std_logic;
    start        : in  std_logic;
    stop         : in  std_logic;
    setmin       : in  std_logic;
    sethour      : in  std_logic;
    sel          : out std_logic_vector(2 downto 0);  ------show setting value
    cout_inc     : out std_logic_vector(3 downto 0);
    cout_seg     : out std_logic_vector(6 downto 0);
    cout_seg_10s : out std_logic_vector(6 downto 0);
    cout_seg_1m  : out std_logic_vector(6 downto 0);
    cout_seg_10m : out std_logic_vector(6 downto 0);
    cout_seg_1h  : out std_logic_vector(6 downto 0);
    cout_seg_10h : out std_logic_vector(6 downto 0));
end counter_4bit;


architecture rtl of counter_4bit is
  

  signal Lsec       : std_logic_vector(3 downto 0) := "0000";
  signal Hsec       : std_logic_vector(3 downto 0) := "0000";
  signal Lmin       : std_logic_vector(3 downto 0) := "0000";
  signal Hmin       : std_logic_vector(3 downto 0) := "0000";
  signal Lhour      : std_logic_vector(3 downto 0) := "0000";
  signal Hhour      : std_logic_vector(3 downto 0) := "0000";
  signal carry      : std_logic;
  signal carrym     : std_logic;
  signal clk_1_tmp      : std_logic;
  signal clk_100_tmp    : std_logic;
  signal clk_switch : std_logic:='0';
  signal data       : std_logic_vector(3 downto 0);


  component clk_gen
    port (
      clk, reset, power : in  std_logic;
      clk_1, clk_100    : out std_logic);
  end component;

  component seg_dec
    port (
      cin  : in  std_logic_vector(3 downto 0);
      cout : out std_logic_vector(6 downto 0));
  end component;

  component newhour
    port (
      carrym       : in  std_logic;
      reset        : in  std_logic;
      Hhour, Lhour : out std_logic_vector(3 downto 0));
  end component;

  component newminute
    port (
      carry, reset, clk1, sethour : in  std_logic;
      Lmin, Hmin                  : out std_logic_vector(3 downto 0);
      carrym                      : out std_logic);
  end component;

  component newsecond
    port (
      clk, reset, clk1, setmin : in  std_logic;
      Lsec, Hsec               : out std_logic_vector(3 downto 0);
      carry                    : out std_logic);
  end component;

  component m6_1scan
    port (
      reset                        : in  std_logic;
      clkscan                      : in  std_logic;
      in1, in2, in3, in4, in5, in6 : in  std_logic_vector(3 downto 0);
      data                         : out std_logic_vector(3 downto 0);
      sel                          : out std_logic_vector(2 downto 0));
  end component;
  

  
begin

  u0 : clk_gen port map (
    clk     => clk,
    clk_1   => clk_1_tmp,
    clk_100 => clk_100_tmp,
    reset   => reset,
    power   => power);


  u1 : seg_dec port map (
    cin  => Lsec,
    cout => cout_seg);

  u2 : seg_dec port map (
    cin  => Hsec,
    cout => cout_seg_10s);
  u3 : seg_dec port map (
    cin  => Lmin,
    cout => cout_seg_1m);
  u4 : seg_dec port map (
    cin  => Hmin,
    cout => cout_seg_10m);
  u5 : seg_dec port map (
    cin  => Lhour,
    cout => cout_seg_1h);
  u6 : seg_dec port map (
    cin  => Hhour,
    cout => cout_seg_10h);

  u7 : newsecond port map (
    clk    => clk_1_tmp,
    clk1   => clk,
    setmin => setmin,
    reset  => reset,
    Lsec   => Lsec,
    Hsec   => Hsec,
    carry  => carry);

  u8 : newminute port map (
    carry   => carry,
    sethour => sethour,
    clk1    => clk,
    reset   => reset,
    Lmin    => Lmin,
    Hmin    => Hmin,
    carrym  => carrym);

  u9 : newhour port map (
    carrym => carrym,
    reset  => reset,
    Lhour  => Lhour,
    Hhour  => Hhour);

  u10 : m6_1scan port map (
    reset   => reset,
    clkscan => clk,
    in1     => Lsec,
    in2     => Hsec,
    in3     => Lmin,
    in4     => Hmin,
    in5     => Lhour,
    in6     => Hhour,
    sel     => sel,
    data    => data);                   --puzzle.



  cout_inc <= Lsec;

  process (power, stop,start)  -------------------stop can be in or not.
  begin
    
    if power = '1'then
      clk_switch <= clk_100_tmp after 100 ns;
    elsif stop = '1' then
      clk_switch <= '0' after 100 ns ;
    elsif start='1' then
       clk_switch <= clk_1_tmp after 100 ns;
    else
       clk_switch <=clk_switch;
    end if;
  end process;

end rtl;