program-s.vhd

来自「last time when i came here to find some 」· VHDL 代码 · 共 50 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
  port (clk,reset,clk1:in std_logic;
        setmin        : in std_logic :='0';
        Lsec,Hsec: out std_logic_vector(3 downto 0);
        carry: out std_logic);
end newsecond;
architecture t1 of newsecond is
signal sect1: std_logic_vector(3 downto 0);
signal sect2 : std_logic_vector(3 downto 0);
--signal delay_counter : std_logic_vector(24 downto 0):="0000000000000000000000000";
begin
process(reset,clk)
    begin
    if reset='1' then
       sect1<="0000";
       sect2<="0000";
    elsif setmin='1' then
      carry<=clk1;
--       delay_counter<=(others=>'0');
    elsif (clk'event and clk='1') then
--      if delay_counter="1111111111111111111111111" then
--         delay_counter<=(others=>'0');--------this is very iportant being here---------------------------------
        if sect1="1001" then
           sect1<="0000";
                                      -- not to be here delay_counter<=(others=>'0');
            if sect2="0101"  then
               sect2<="0000";
            else
              sect2<=sect2+1;
            end if;
        else
          sect1<=sect1+1;
         end if;
--      else
--          delay_counter <= delay_counter+1;
--        end if;
          if (sect1="1001" and sect2="0101") then
            carry<='1';
        else
            carry<='0';
        end if;
    end if;
    end process;
        Lsec<=sect1;
        Hsec<=sect2;
end t1;