clk_gen.vhd

来自「last time when i came here to find some 」· VHDL 代码 · 共 75 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;


entity clk_gen is
  port (clk, reset, power : in  std_logic;
        clk_1             : out std_logic;
        clk_100           : out std_logic);
   
end clk_gen;

architecture Behavioral of clk_gen is
  signal cnt_clk_100 : std_logic_vector(3 downto 0);
  signal cnt_clk_1   : std_logic_vector(3 downto 0);
  signal p           : std_logic;


  

begin

  process (clk, reset)
  begin
    if reset = '1' then
      cnt_clk_1 <= "0000";
      clk_1     <= '0';
    elsif (clk'event and clk = '1') then
      if cnt_clk_1 = "1111" then  -- 100 ms at 1MHz clock
        clk_1     <= '1';
        cnt_clk_1 <= "0000";
        
      else
        cnt_clk_1 <= cnt_clk_1 + 1;
        clk_1     <= '0';
      end if;
    end if;
  end process;

  process (clk, reset, p)
  begin
    if reset = '1' then
      cnt_clk_100 <= "0000";
      clk_100     <= '0';
    elsif clk = '1' and clk'event and p = '1' then
      if cnt_clk_100 = "1111"then  -- 1 s at 1MHz clock

        clk_100     <= '1';
        cnt_clk_100 <= "0000";
      else
        cnt_clk_100 <= cnt_clk_100 +1;
        clk_100     <= '0';
      end if;

      
    end if;
  end process;

  process (clk, reset, power)
  begin
    if reset = '1' then
      p <= '0';
    elsif clk = '1' and clk'event then
        if power = '1' then
          p <= '1';
        else
          p <= p;
      end if;
    end if;
  end process;

end Behavioral;