os_cpu.h

ARM7 based on STR71x, UCOS migration

/********************************************************************************************************
												uC/OS-II
										The Real-Time Kernel

								(c) Copyright 1992-2004, Micrium, Weston, FL
											All Rights Reserved

 File : OS_CPU.H
 By   : Yujun Huanng
********************************************************************************************************/

#ifndef OS_CPU_H
#define OS_CPU_H

#ifdef  OS_CPU_GLOBALS
	#define OS_CPU_EXT
#else
	#define OS_CPU_EXT  extern
#endif

/********************************************************************************************************
												DATA TYPES
											(Compiler Specific)
********************************************************************************************************/
typedef unsigned char  BOOLEAN;					// 布尔变量
typedef unsigned char  INT8U;					// 无符号8位整型变量			(Unsigned 8 bit quantity)
typedef signed   char  INT8S;					// 有符号8位整型变量			(Signed 8 bit quantity)
typedef unsigned short INT16U;					// 无符号16位整型变量			(Unsigned 16 bit quantity)
typedef signed   short INT16S;					// 有符号16位整型变量			(Signed 16 bit quantity)
typedef unsigned int   INT32U;					// 无符号32位整型变量			(Unsigned 32 bit quantity)
typedef signed   int   INT32S;					// 有符号32位整型变量			(Signed 32 bit quantity)
typedef float          FP32;					// 单精度浮点数(32位长度)		(Single precision floating point)
typedef double         FP64;					// 双精度浮点数(64位长度)		(Double precision floating point)

typedef unsigned int   OS_STK;					// 堆栈是32位宽度				(Each stack entry is 32-bit wide)
typedef unsigned int   OS_CPU_SR;				// ARM的状态寄存器(PSR = 32位)	(Define size of CPU status register (PSR = 32 bits))

#define BYTE           INT8S                     /* Define data types for backward compatibility ...   */
#define UBYTE          INT8U                     /* ... to uC/OS V1.xx.  Not actually needed for ...   */
#define WORD           INT16S                    /* ... uC/OS-II.                                      */
#define UWORD          INT16U
#define LONG           INT32S
#define ULONG          INT32U

/********************************************************************************************************
												ARM

 Method #1:  Disable/Enable interrupts using simple instructions.  After critical section, interrupts
             will be enabled even if they were disabled before entering the critical section.
             NOT IMPLEMENTED

 Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In other words, if 
             interrupts were disabled before entering the critical section, they will be disabled when
             leaving the critical section.
             NOT IMPLEMENTED

 Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
             into the CPU's status register.
********************************************************************************************************/
#define  OS_CRITICAL_METHOD		3		// 选择开、关中断的方式		(Select the mode of Open/Close interrupts)
#define	OS_IntOn	0x03
#define OS_IntOff	0x00
//#define OS_EnterOS	0x00

#if OS_CRITICAL_METHOD == 3
//	#define  OS_ENTER_CRITICAL()  { OS_CPU_ICR_Save(); }
//	#define  OS_EXIT_CRITICAL()   { OS_CPU_ICR_Restore(); }

	#define  OS_ENTER_CRITICAL()  { cpu_sr = OS_CPU_ICR_Save(); }
	#define  OS_EXIT_CRITICAL()   { OS_CPU_ICR_Restore(cpu_sr); }
#endif

/********************************************************************************************************
										ARM Miscellaneous
********************************************************************************************************/
#define OS_STK_GROWTH		1			// ARM的堆栈是从上往下长的	(Stack grows from HIGH to LOW memory on ARM)

#define OS_TASK_SW()		OSCtxSw()



//********************************************************************************************************
//										GLOBAL VARIABLES
//********************************************************************************************************

//********************************************************************************************************
//										PROTOTYPES
//********************************************************************************************************
#if OS_CRITICAL_METHOD == 3				// Allocate storage for CPU status register
	OS_CPU_SR OS_CPU_SR_Save(void);
	void OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
#endif

//********************************************************************************************************
//										defined in os_cpu_a.s
//********************************************************************************************************
void OS_CPU_IRQ_ISR(void);				// See OS_CPU_A.S
void OS_CPU_FIQ_ISR(void);

extern void OSCtxSw(void);				// task switch routine
extern void OSIntCtxSw(void);			// interrupt context switch
extern void OSTickISR(void);			// timer interrupt routine

//********************************************************************************************************
//										defined in 71_vect.s
//********************************************************************************************************
void IRQHandler(void);		// See BSP code
void FIQHandler(void);

#endif