📄 hard_define.h
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#define HTIM_R ( ( HREGPTR )( HTIM_BASE + 0x0C ) )
#define HTIM_ENABLE { *MCU_TMEN = 0x04; }
#define HTIM_DISABLE { *MCU_TMDIS = 0x04; }
/* Use timer 3 as the communication hardware control timer */
/* Com. control timer base address */
#define COMTIM_BASE MCU_TC3_BASE
/* Control register */
#define COMTIM_CON ( ( BREGPTR )( COMTIM_BASE ) )
/* Status register */
#define COMTIM_ST ( ( BREGPTR )( COMTIM_BASE + 0x04 ) )
/* Timer counter */
#define COMTIM_C ( ( HREGPTR )( COMTIM_BASE + 0x08 ) )
/* Timer register */
#define COMTIM_R ( ( HREGPTR )( COMTIM_BASE + 0x0C ) )
#define COMTIM_ENABLE { *MCU_TMEN = 0x08; }
#define COMTIM_DISABLE { *MCU_TMDIS = 0x08; }
/* Hardware timer controls */
#define INIT_HTIM { *HTIM_CON = 0x00; \
*HTIM_ST = 0x01; \
*HTIM_C = HTIMER_TICK; \
ENABLE_ITIM \
HTIM_ENABLE }
/* *HTIM_CON = 0x00; Use SYSCLK as basic timing unit, */
/* i.e. 41.67 ns per timer tick at 24MHz */
/* *HTIM_ST = 0x01; Clear any possible overflow event before */
/* *HTIM_C = HTIMER_TICK; HTIM_R is written with the same value */
/* automatically by the MCU */
/* ENABLE_ITIM Enable the timer interrupt */
/* HTIM_ENABLE Start the timer counting */
/* Communication timer controls */
#define INIT_COMTIM { *COMTIM_ST = 0x01; \
COMTIM_DISABLE \
*COMTIM_C = 0x0000; \
ENABLE_ICTM }
/* *COMTIM_ST = 0x01; Clear any possible overflow event before */
/* COMTIM_DISABLE Clear the timer first */
/* *COMTIM_C = 0x0000; */
/* ENABLE_ICTM Enable the control timer interrupt */
#define START_COMTIM(offset,t) {*COMTIM_CON = offset; \
*COMTIM_C = t; \
COMTIM_ENABLE }
#define STOP_COMTIM {COMTIM_DISABLE \
*COMTIM_C = 0x0000; }
/*
*************************************************
Section 1.9 -- Serial Port Hardware Control
*************************************************
*/
/*
*************************************************
Section 1.9.1 -- Register Coding Definitions
*************************************************
*/
/* FCR bits */
#define FCR_RFTL_MASK 0xC0
#define FCR_RFTL_1 0x00
#define FCR_RFTL_4 0x40
#define FCR_RFTL_8 0x80
#define FCR_RFTL_16 0xC0
#define FCR_DMS_BIT 0x08
#define FCR_TFR_BIT 0x04
#define FCR_RFR_BIT 0x02
#define FCR_FIFOE_BIT 0x01
/* LCR bits */
#define LCR_DLAB_BIT 0x80
#define LCR_BC_BIT 0x40
#define LCR_SP_BIT 0x20
#define LCR_EPS_BIT 0x10
#define LCR_PE_BIT 0x08
#define LCR_SBS_BIT 0x04
#define LCR_WLS_MASK 0x03
#define LCR_WLS_5 0x00
#define LCR_WLS_6 0x01
#define LCR_WLS_7 0x02
#define LCR_WLS_8 0x03
/* LSR bits */
#define LSR_RFR_BIT 0x80
#define LSR_TEMT_BIT 0x40
#define LSR_THRE_BIT 0x20
#define LSR_BI_BIT 0x10
#define LSR_FE_BIT 0x08
#define LSR_PE_BIT 0x04
#define LSR_OE_BIT 0x02
#define LSR_RXERR_MASK 0x0E
#define LSR_DR_BIT 0x01
/* MCR bits */
#define MCR_LOOP_BIT 0x10
#define MCR_OUT2_BIT 0x08
#define MCR_OUT1_BIT 0x04
#define MCR_CTS_BIT 0x02
#define MCR_DSR_BIT 0x01
/* MSR bits */
#define MSR_RI_BIT 0x80
#define MSR_DCD_BIT 0x40
#define MSR_DTR_BIT 0x20
#define MSR_RTS_BIT 0x10
#define MSR_TERI_BIT 0x08
#define MSR_DDCD_BIT 0x04
#define MSR_DDTR_BIT 0x02
#define MSR_DRTS_BIT 0x01
/* IIR bits */
#define IIR_FIFOEN_MASK 0xC0
#define IIR_INTID_MASK 0x0E
#define IIR_INTID_LS 0x06
#define IIR_INTID_RBF 0x04
#define IIR_INTID_CTI 0x0C
#define IIR_INTID_TBE 0x02
#define IIR_INTID_MDS 0x00
#define IIR_INT_MASK 0x0F
#define IIR_INT_LS 0x06
#define IIR_INT_RBF 0x04
#define IIR_INT_CTI 0x0C
#define IIR_INT_TBE 0x02
#define IIR_INT_MDS 0x00
#define IIR_INT_RX_MASK 0x07
#define IIR_INT_RX 0x04
#define IIR_INTP_BIT 0x01
/* IER bits */
#define IER_EDSSI_BIT 0x08
#define IER_ELSI_BIT 0x04
#define IER_ETBEI_BIT 0x02
#define IER_ERBFI_BIT 0x01
/* DLL bits */
/* SYSCLK 24MHz */
#define DLL_24_300 0x88
#define DLL_24_600 0xC4
#define DLL_24_1200 0xE2
#define DLL_24_2400 0x71
#define DLL_24_4800 0x39
#define DLL_24_9600 0x9C
#define DLL_24_19200 0x4E
#define DLL_24_38400 0x27
#define DLL_24_57600 0x1A
#define DLL_24_115200 0x0D
/* DLM bits */
/* SYSCLK 24MHz */
#define DLM_24_300 0x13
#define DLM_24_600 0x09
#define DLM_24_1200 0x04
#define DLM_24_2400 0x02
#define DLM_24_4800 0x01
#define DLM_24_9600 0x00
#define DLM_24_19200 0x00
#define DLM_24_38400 0x00
#define DLM_24_57600 0x00
#define DLM_24_115200 0x00
/* Baud rate settings */
#define BAUD_RATE_24_300 ( DLL_24_300 | ( DLM_24_300 << 8 ) )
#define BAUD_RATE_24_600 ( DLL_24_600 | ( DLM_24_600 << 8 ) )
#define BAUD_RATE_24_1200 ( DLL_24_1200 | ( DLM_24_1200 << 8 ) )
#define BAUD_RATE_24_2400 ( DLL_24_2400 | ( DLM_24_2400 << 8 ) )
#define BAUD_RATE_24_4800 ( DLL_24_4800 | ( DLM_24_4800 << 8 ) )
#define BAUD_RATE_24_9600 ( DLL_24_9600 | ( DLM_24_9600 << 8 ) )
#define BAUD_RATE_24_19200 ( DLL_24_19200 | ( DLM_24_19200 << 8 ) )
#define BAUD_RATE_24_38400 ( DLL_24_38400 | ( DLM_24_38400 << 8 ) )
#define BAUD_RATE_24_57600 ( DLL_24_57600 | ( DLM_24_57600 << 8 ) )
#define BAUD_RATE_24_115200 ( DLL_24_115200 | ( DLM_24_115200 << 8 ) )
/* Data format settings */
#define DATA_FORMAT_8N1 ( LCR_WLS_8 )
#define DATA_FORMAT_7E1 ( LCR_WLS_7 | LCR_EPS_BIT | LCR_PE_BIT )
#define DATA_FORMAT_7O1 ( LCR_WLS_7 | LCR_PE_BIT )
#define DATA_FORMAT_8N2 ( LCR_WLS_8 | LCR_SBS_BIT )
#define DATA_FORMAT_8E1 ( LCR_WLS_8 | LCR_EPS_BIT | LCR_PE_BIT )
#define DATA_FORMAT_8O1 ( LCR_WLS_8 | LCR_PE_BIT )
/* CSR bits */
#define CSR_BGCLK_MASK 0x03
#define CSR_BGCLK_SYSCLK 0x00
#define CSR_BGCLK_2TBCCLK 0x01
#define CSR_BGCLK_4TBCCLK 0x02
#define CSR_BGCLK_8TBCCLK 0x03
/*
*************************************************
Section 1.9.2 -- Macro Definitions
*************************************************
*/
#define SP_RTS_ON ( *MCU_MSR & MSR_RTS_BIT )
#define SP_RTS_OFF ( ( *MCU_MSR & MSR_RTS_BIT ) == 0x00 )
#define SP_RTS_CHANGED ( *MCU_MSR & MSR_DRTS_BIT )
#define SP_DTR_ON ( *MCU_MSR & MSR_DTR_BIT )
#define SP_DTR_OFF ( ( *MCU_MSR & MSR_DTR_BIT ) == 0x00 )
#define SP_DTR_CHANGED ( *MCU_MSR & MSR_DDTR_BIT )
#define SP_NO_RXERR ( ( *MCU_LSR & LSR_RXERR_MASK ) == 0x00 )
#define SP_TXFIFO_EMPTY ( *MCU_LSR & LSR_THRE_BIT )
#define SP_RXFIFO_EMPTY ( ( *MCU_LSR & LSR_DR_BIT ) == 0x00 )
#define SP_SET_CTS_ON ( *MCU_MCR |= MCR_CTS_BIT )
#define SP_SET_CTS_OFF ( *MCU_MCR &= ~MCR_CTS_BIT )
#define SP_SET_CTS_DSR_ON { *MCU_MCR = MCR_CTS_BIT | MCR_DSR_BIT; }
#define SP_BINT_ENABLE { *MCU_IER = IER_ETBEI_BIT | IER_ERBFI_BIT; }
#define SP_NO_DATA_TX ( *MCU_LSR & LSR_TEMT_BIT )
#define SP_TX_BUF ( *MCU_THR )
#define SP_RX_BUF ( *MCU_RBR )
#define SP_INTID_RBE IIR_INTID_RBF
#define SP_INTID_CTI IIR_INTID_CTI
#define SP_INTID_TBE IIR_INTID_TBE
#define SP_INTID ( *MCU_IIR & ( IIR_INTID_MASK | IIR_INTP_BIT ) )
#define INIT_SER { *MCU_FCR = FCR_RFTL_8 | FCR_TFR_BIT | \
FCR_RFR_BIT | FCR_FIFOE_BIT; \
*MCU_LCR = LCR_DLAB_BIT; }
/* *MCU_FCR = FCR_RFTL_8 | FCR_TFR_BIT | FCR_RFR_BIT | FCR_FIFOE_BIT; */
/* FIFO level 8, Reset TX/RX FIFO, FIFO */
/* Enabled */
/* *MCU_LCR = LCR_DLAB_BIT; Enable DLL/DLM access */
#define SP_SET_DATA_FORMAT(d) { *MCU_LCR = d; }
#define SP_SET_BAUD_RATE(b) { *MCU_DLL = ( b & 0xFF ); \
*MCU_DLM = ( b >> 8 ); }
#endif
/*
*********************************
Section 2 -- Constant Definitions
*********************************
*/
#endif /* End of definitions _INC_STR710FZ2T6HARDDEF */
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