hard_define.h

ARM7 based on STR71x, UCOS migration

/*
 *****************************************************************************
 *                                                                           *
 *  2.4GHz Spread Spectrum Purpletooth 3rd Generation Wireless Modem         *
 *                                                                           *
 *  Copyright (C) 2001-2004 REnex Technology Limited.  All rights reserved.  *
 *  No part of this document may be reproduced or utilized in any form or by *
 *  any means, electronic or mechanical, including photocopying and microfilm*
 *  , without permission in writing from REnex Technology Limited.           *
 *                                                                           *
 *****************************************************************************
 *                                                                           *
 *  Filename:   STR710FZ2T6HardDef.h                                         *
 *  Date:       Aug 30, 2004                                                 *
 *  Description:Hardware platform control definitions                        *
 *  Version:    WM02/V2.00                                                   *
 *  Hardware:   BBM0110                                                      *
 *  Remarks:    For STR710FZ2T6 only                                         *
 *                                                                           *
 *****************************************************************************
 */
#ifndef HARD_DEFINE_H
#define HARD_DEFINE_H

/*
 *************************************************
 Section 1 -- Hardware Control Configurations
 *************************************************
 */

/*
 *************************************************
 Section 1.1 -- Panel Control
 *************************************************
 */
#define BUTTON_PRESSED     
#define CONFIG_BUTTON_FSR  

#define DEBUG_LED

#ifdef DEBUG_LED
                                /* OK LED indication P2.12                  */
#define OK_LED_ON          { *MCU_GPIO2_PD |= 0x1000; }
#define OK_LED_OFF         { *MCU_GPIO2_PD &= ~0x1000; }
#define OK_LED_TOGGLE      { *MCU_GPIO2_PD ^= 0x1000; }

                                /* Power on LED indication P2.13            */
#define PWR_LED_ON         { *MCU_GPIO2_PD |= 0x2000; }
#define PWR_LED_OFF        { *MCU_GPIO2_PD &= ~0x2000; }
#define PWR_LED_TOGGLE     { *MCU_GPIO2_PD ^= 0x2000; }

                                /* Rx LED indication P2.14                  */
#define RX_LED_ON          { *MCU_GPIO2_PD |= 0x4000; }
#define RX_LED_OFF         { *MCU_GPIO2_PD &= ~0x4000; }
#define RX_LED_TOGGLE      { *MCU_GPIO2_PD ^= 0x4000; }

                                /* Tx LED indication P2.15                  */
#define TX_LED_ON          { *MCU_GPIO2_PD |= 0x8000; }
#define TX_LED_OFF         { *MCU_GPIO2_PD &= ~0x8000; }
#define TX_LED_TOGGLE      { *MCU_GPIO2_PD ^= 0x8000; }
#else
/* All LED control in LedCtrl() */
#define OK_LED_ON
#define OK_LED_OFF
#define OK_LED_TOGGLE
#define PWR_LED_ON
#define PWR_LED_OFF
#define PWR_LED_TOGGLE
#define RX_LED_ON
#define RX_LED_OFF
#define RX_LED_TOGGLE
#define TX_LED_ON
#define TX_LED_OFF
#define TX_LED_TOGGLE
#endif

#define ALL_LED_EN         { OK_LED_EN        \
                             PWR_LED_EN       \
                             RX_LED_EN        \
                             TX_LED_EN        }

#define ALL_LED_ON         { OK_LED_ON        \
                             PWR_LED_ON       \
                             RX_LED_ON        \
                             TX_LED_ON        }

/*
 *************************************************
 Section 1.2 -- Display Port Control
 *************************************************
 */
#define DIS_DATA_PORT                                 /* LCD data port      */
#define DIS_CMD_PORT                                  /* LCD command port   */

/*
 *************************************************
 Section 1.3 -- WatchDog Timer Control
 *************************************************
 */
/* Start WatchDog timer */
#define WATCHDOG_START     { *MCU_WDG_CR = 0x0000;                           \
                             *MCU_WDG_CR = 0x0002;                           }

/*
 *************************************************
 Section 1.4 -- DSS Hardware Control
 *************************************************
 */
                                       /* P7.1 for DSS reset                */
#define RESET_EN_DSS       
#define RESET_DIS_DSS      
                                       /* Not used, for compatibility only  */
#define BUS_ISO_EN_DSS     
#define BUS_ISO_DIS_DSS    
                                       /* Not used, for compatibility only  */
#define POWER_UP_DSS       
#define POWER_DN_DSS       
                                     
#define DSS_BASE           0x64000000  /* DSS base address (bank 2)         */
/* Note: Address of DSS register left-shited by 1 bit to allign with MCU    */
/* are half-word data access                                                */

/*
 *************************************************
 Section 1.5 -- I2C Hardware Control
 *************************************************
 */
/* Undefined module */

/*
 *************************************************
 Section 1.6 -- DM9K Hardware Control
 *************************************************
 */
/* Host address map for DM9000 register definitions */
#define DM9K_BASE          0x66000000  /* I/O Base Address                  */
#define DM9K_ADDR_OFFSET   0           /* ADDR Register I/O address offset  */
#define DM9K_DATA_OFFSET   4           /* DATA Register I/O address offset  */
                                       /* Addr I/O                          */
#define DM9K_ADDR_ADDRESS  ( ( BREGPTR )( DM9K_BASE + DM9K_ADDR_OFFSET ) )
                                       /* Data I/O                          */
#define DM9K_DATA_ADDRESS  ( ( BREGPTR )( DM9K_BASE + DM9K_DATA_OFFSET ) )
                                       /* DM9K Clock Control P4.0           */
#define DM9K_CLOCK_ON      
#define DM9K_CLOCK_OFF     
                                       /* DM9K Reset P2.1                   */
#define DM9K_HARD_RESET    
#define DM9K_ON            

/*
 *************************************************
 Section 1.7 -- RF Hardware Control
 *************************************************
 */
#ifdef TEMPXXX
#define RF_PA_PWR_ON       
#define RF_PA_PWR_OFF      
#define RF_PA_PWR_EN       
                                      /* Timer 0 (P3.2) for power amp. 1    */
#define RF_PA1_PC_CTRL_EN  { *MCU_PFS1 |= 0x0400;                    \
                             *MCU_PM1  |= 0x0400;                    \
                             *MCU_PO1  &= ~0x0400;                   }
#define RF_PA1_PC_EN       { *MCU_TM0CON  = 0x10;                    \
                             *MCU_TM0IOLV = 0x00;                    \
                             *MCU_TM0C    = RF_PC_PERIOD;            }

#define SET_RF_PA1_PC(lvl) { *MCU_TM0GR = 0xFFFF - ( lvl & 0x0F ); }
#ifndef WM014X
                                      /* Timer 1 (P3.3) for power amp. 2    */
#define RF_PA2_PC_CTRL_EN  { *MCU_PFS1 |= 0x0800;                    \
                             *MCU_PM1  |= 0x0800;                    \
                             *MCU_PO1  &= ~0x0800;                   }
#define RF_PA2_PC_EN       { *MCU_TM1CON  = 0x10;                    \
                             *MCU_TM1IOLV = 0x00;                    \
                             *MCU_TM1C    = RF_PC_PERIOD;            }

#define SET_RF_PA2_PC(lvl) { *MCU_TM1GR = 0xFFFF - ( lvl & 0x0F ); }
#endif
#ifdef WM014X
#define RF_PA_ON           { *MCU_TMEN  = 0x01;                      \
                             *MCU_PFS1 |= 0x0400;                    }
#define RF_PA_OFF          { *MCU_PFS1 &= ~0x0400;                   \
                             *MCU_TMDIS = 0x01;                      }
#else
#define RF_PA_ON           { *MCU_TMEN  = 0x03;                      \
                             *MCU_PFS1 |= 0x0C00;                    }
#define RF_PA_OFF          { *MCU_PFS1 &= ~0x0C00;                   \
                             *MCU_TMDIS = 0x03;                      }
#endif

/* RF receiver gain control */
#ifdef WM014X
                                      /* Timer 1 (P3.3) for rx gain control */
#define RF_LNA_PC_CTRL_EN  { *MCU_PFS1 |= 0x0800;                    \
                             *MCU_PM1  |= 0x0800;                    \
                             *MCU_PO1  &= ~0x0800;                   }
#define RF_LNA_PC_EN       { *MCU_TM1CON  = 0x10;                    \
                             *MCU_TM1IOLV = 0x00;                    \
                             *MCU_TM1C    = RF_LNA_PC_PERIOD;        }

#define SET_RF_LNA_PC(lvl) { *MCU_TM1GR = 0xFFFF - ( lvl & 0x0F );}

#define RF_LNA_CTRL_ON     { *MCU_TMEN  = 0x02;                      \
                             *MCU_PFS1 |= 0x0800;                    }
#define RF_LNA_ON          { SET_RF_LNA_PC( RF_LNA_PC_MAX ) }
#define RF_LNA_OFF         { SET_RF_LNA_PC( RF_LNA_PC_MIN ) }
#endif

/* Demodulator module */
                                      /* P7.2 for demodulator reset         */
#define RESET_EN_DEMOD     { *MCU_P7O &= ~0x04; }
#define RESET_DIS_DEMOD    { *MCU_P7O |= 0x04; }

/* PLL programming control timer */
/* Use timer 3 as the PLL programming control timer */
                                       /* PLL control timer base address    */
#define PLLTIM_BASE        MCU_TC3_BASE        
                                       /* Control register                  */
#define PLLTIM_CON         ( ( BREGPTR )( PLLTIM_BASE ) )
                                       /* Status register                   */
#define PLLTIM_ST          ( ( BREGPTR )( PLLTIM_BASE + 0x04 ) )
                                       /* Timer counter                     */
#define PLLTIM_C           ( ( HREGPTR )( PLLTIM_BASE + 0x08 ) )
                                       /* Timer register                    */
#define PLLTIM_R           ( ( HREGPTR )( PLLTIM_BASE + 0x0C ) )
#define PLLTIM_ENABLE      { *MCU_TMEN  = 0x08; }
#define PLLTIM_DISABLE     { *MCU_TMDIS = 0x08; }

/*
 *************************************************
 Section 1.8 -- Timer Hardware Control
 *************************************************
 */
/* Timer 2 as the hardware timer */
                                       /* Hardware timer base address       */
#define HTIM_BASE          MCU_TC2_BASE
                                       /* Control register                  */
#define HTIM_CON           ( ( BREGPTR )( HTIM_BASE ) )
                                       /* Status register                   */
#define HTIM_ST            ( ( BREGPTR )( HTIM_BASE + 0x04 ) )
                                       /* Timer counter                     */
#define HTIM_C             ( ( HREGPTR )( HTIM_BASE + 0x08 ) )
                                       /* Timer register                    */