📄 tmdlmbs2_0119.rgd
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//-----------------------------------------------------------------------------
// $Header: /usr/ryhti/tmdlMbs/src/tmdlMbs0119.rgd 1 6/18/02 9:44a Bryhti $
// (C) Copyright 1999 Philips Semiconductors, All rights reserved
//
// This source code and any compilation or derivative thereof is the sole
// property of Philips Corporation and is provided pursuant to a Software
// License Agreement. This code is the proprietary information of Philips
// Corporation and is confidential in nature. Its use and dissemination by
// any party other than Philips Corporation is strictly limited by the
// confidential information provisions of the Agreement referenced above.
//-----------------------------------------------------------------------------
// FILE NAME: tmdlMbs0119.rgd
//
// DESCRIPTION: Register descriptor file for the DVP3218 chip, aka VIPER.
//
// Use the RGD tool to generate a header file from this
// descriptor file, e.g.
//
// rgd BigEndian=? tmhw.rgd tmdlMbs0119.rgd > tmdlMbs0119.mio
//
// OR
//
// awk -f rgd.awk -v BigEndian=? tmhw.rgd tmdlMbs0119.rgd > tmdlMbs0119.mio
//
// ? 0 => little endian
// 1 => big endian
//
// DOCUMENT REF: DVP Coding Guidelines Specification
// rgd.txt
//
//-----------------------------------------------------------------------------
//
// Use FILE keyword to make sure section
// #ifndef _TMHW3218_MIO_SEEN
// #define _TMHW3218_MIO_SEEN
// ..
// #endif
// gets added by RGD tool.
//
file tmdlMbs0119.mio
//-----------------------------------------------------------------------------
// MBS MMIO BLOCK
//-----------------------------------------------------------------------------
//
// Memory Based Scaler, based on rev 0.90 design specification,
// compatable with 0.81 Quickturn/Ikos netlist
//
module MBS tmdlMbsRegs 0119
struct _mbsCtrl{ // MBS control register subset
//
val MBS_REGOFFSET_MODE_CTRL 0
bits modeCtrl 00000 // MBS Mode Control
01:00 horzProcessingMode // horizontal process mode
val MBS_HPM_BYPASS 0 // bypass
val MBS_HPM_CSM 1 // color space matrix mode
val MBS_HPM_NORMAL 2 // normal polyphase mode
val MBS_HPM_TRANSPOSED 3 // transposed polyphase mode
:02 horzClrClampMode // CCIR clamping range
val MBS_HCSC_CLAMP_YUV 0 // clamp in YUV color space
val MBS_HCSC_CLAMP_RGB 1 // clamp in RGB color space
:03 horzClampMode
val MBS_HCM_NONE 0 // no clamp (0..255)
val MBS_HCM_CCIR 1 // use CCIR clr space clamp
05:04 vertProcessingMode // vertical processing mode
val MBS_VPM_BYPASS 0 // bypass
val MBS_VPM_NORMAL 2 // normal polyphase mode
:06 vertClrClampMode // CCIR clamping range
val MBS_VCSC_CLAMP_YUV 0 // clamp in YUV color space
val MBS_VCSC_CLAMP_RGB 1 // clamp in RGB color space
:07 vertClampMode
val MBS_VCM_NONE 0 // no clamp (0..255)
val MBS_VCM_CCIR 1 // use CCIR clr space clamp
09:08 decimationMode
val MBS_DM_BYPASS 0 // bypass decimation filter
val MBS_DM_COSITED_SUB 1 // co-sited (sub sample)
val MBS_DM_COSITED_LOW 2 // co-sited (low pass)
val MBS_DM_INTERSPERSED 3 // interspersed
:10 decimClampMode
val MBS_DCM_NONE 0 // no clamp (0..255)
val MBS_DCM_CCIR 1 // use CCIR range
13:12 interpolationMode
val MBS_IM_BYPASS 0 // bypass
val MBS_IM_COSITED 2 // co-sited
val MBS_IM_INTERSPERSED 3 // interspersed
:14 interpolClampMode
val MBS_ICM_NONE 0 // no clamp (0..255)
val MBS_ICM_CCIR 1 // use CCIR range
:16 softReset // write '1' will cause reset
:17 skipTask // write '1' to skip cur task
:18 noAutoSkip // continue until pipeline
// stages are idle
:19 maskTaskInts // mask task done interrupts
21:20 coefLutMode // coeff lookup table
// access mode
val MBS_LUT_MODE_SEPARATE 0
val MBS_LUT_MODE_COPY_2_TO_3 1 // table 2 copied to 3
val MBS_LUT_MODE_COPY_1_TO_2 2 // table 1 copied to 2
val MBS_LUT_MODE_COPY_1_TO_2_3 3 // table 1 copied to 2 & 3
23:22 msa3 // MSA 3-field mode
val MBS_MSA3_NORMAL 0
val MBS_MSA3_ENHANCED 1
val MBS_MSA3_DYNAMIC 2
val MBS_MSA3_DYNAMIC_ENHANCED 3
25:24 deinterlacingMode
val MBS_DIM_NONE 0 // no deinterlacing
val MBS_DIM_MEDIAN 1 // vertical temporal median
val MBS_DIM_MAJORITY2FLD 2 // majority selection 2 field
val MBS_DIM_MAJORITY3FLD 3 // majority selection 3 field
:26 eddiEnable // 1: enable EDDI
:27 dimTopIsPrevL // 1: top field is prev luma
// 0: top field is current
:28 dimTopIsPrevC // 1: top field is prev chroma
// 0: top field is current
:29 pnx1500MSA3enhanced
31:30 dataPathSequence
val MBS_DPS_BYPASS 0 // bypass all filter stages
val MBS_DPS_HORZ_BEFORE_VERT 2 // horizontal first
val MBS_DPS_VERT_BEFORE_HORZ 3 // vertical first
val MBS_MODE_CTRL_DEFAULT 0x00004488
//
bits feature 00010
06:04 maxLineLength
:16 horzScaler
:17 vertScaler
:18 deinterlacing
:19 eddi
:20 measurements
//
bits taskFifo 00040
02:00 taskCmd
val MBS_TC_GET_DESCRIPTOR 0 // fetch task desriptor
val MBS_TC_START_SCALING 1 // start with current setup
31:03 taskBaseAddr // task descriptor address
//
bits taskStatus 00044
03:00 taskPendingCount // number of pending tasks
bits lastTask 00048
31:00 taskAddress
//
val MBS_REGOFFSET_INPUT_FORMAT 0x100
bits inputFormat 00100
07:00 format
// applicable to input and output, but not all supported by both
// planar
val MBS_PIXFMT_YUV420_SEMIPLANAR 0x00
val MBS_PIXFMT_YUV420_PLANAR 0x03
val MBS_PIXFMT_YUV422_SEMIPLANAR 0x08
val MBS_PIXFMT_YUV422_PLANAR 0x0b
val MBS_PIXFMT_YUV444_PLANAR 0x0f
val MBS_PIXFMT_RGB888_PLANAR MBS_PIXFMT_YUV444_PLANAR
// packed
val MBS_PIXFMT_YUY2422 0xa0
val MBS_PIXFMT_UYVY422 0xa1
val MBS_PIXFMT_ARGB8888 0xe2
val MBS_PIXFMT_AYUV8444 MBS_PIXFMT_ARGB8888
val MBS_PIXFMT_AVYU8444 0xe3
// indexed
val MBS_PIXFMT_INDEXED_1_BPP 0x24
val MBS_PIXFMT_INDEXED_2_BPP 0x45
val MBS_PIXFMT_INDEXED_4_BPP_A4 0x66
val MBS_PIXFMT_INDEXED_8_BPP_A8 0x87
// compressed (16 bpp)
val MBS_PIXFMT_ARGB4444 0xa9
val MBS_PIXFMT_ARGB4453 0xaa
val MBS_PIXFMT_RGB565 0xad
// variable
val MBS_PIXFMT_VAR32_422 0xe8
val MBS_PIXFMT_VAR16_444 0xac
val MBS_PIXFMT_VAR32_444 0xec
:13 oppositeEndianess // 0: same, 1:opposite
:15 mirrorMode // 0: normal, 1: mirror
31:30 baseAddrMode
val MBS_BAM_SINGLE_SET 0 // progressive or interlaced
val MBS_BAM_ALT_SET_EACH_LINE 1 // field mode
val MBS_INPUT_FORMAT_DEFAULT 0x000000a0
//
bits srcWindowSize 00104
10:00 lineCount // # lines (height)
26:16 lineSize // # pixels per line (width)
val MBS_WINDOW_SIZE_DEFAULT 0x02d001e0
//
bits varInputFormats 00108
04:00 offsetYR // index of MSB position
07:05 sizeYR // #bits-1
12:08 offsetUG
15:13 sizeUG
20:16 offsetVBY2
23:21 sizeVBY2
28:24 offsetAV // alpha
31:29 sizeAV
val MBS_VARIABLE_FORMAT_DEFAULT 0xffe7eff7
//
val MBS_REGOFFSET_SRC_ADDR 0x140
UInt32 srcDmaAddr1 00140
S15 srcLinePitch1 00144 // signed (two's complement)
val MBS_LINE_PITCH1_DEFAULT 0x05a0
//
UInt32 srcDmaAddr2 00148
S15 srcLinePitch2 0014c // signed (two's complement)
val MBS_LINE_PITCH2_DEFAULT 0
//
UInt32 srcDmaAddr3 00150
UInt32 srcDmaAddr4 00154
UInt32 srcDmaAddr5 00158
UInt32 srcDmaAddr6 0015c
//
val MBS_REGOFFSET_HORZ_ZOOM 0x200
bits horzInitialZoom 00200
19:00 scaleFactor
val MBS_HSP_SCALE_UNITY 0x10000
:24 horzDffRuninCrop
:25 horzIffRuninCrop
:26 horzFilterComp
val MBS_HSP_3_COMP 0 // 3 component 6 tap scaling
val MBS_HSP_4_COMP 1 // 4 component 3 tap scaling
:27 horzUVskip
val MBS_HSP_UV_SEQ 0 // normal chroma sequence
val MBS_HSP_UV_SKIP 1 // skip first chroma sample
:28 disableCropping
val MBS_HSP_ENABLE_CROPPING 0
val MBS_HSP_DISABLE_CROPPING 1
31:29 phaseMode
// Phase mode applicable to both horz and vert
val MBS_PM_64_PHASES 0
val MBS_PM_32_PHASES 1
val MBS_PM_16_PHASES 2
val MBS_PM_8_PHASES 3
val MBS_PM_4_PHASES 4
val MBS_PM_2_PHASES 5
val MBS_PM_FIXED_PHASE 6
val MBS_PM_LINEAR_INTERPOLATION 7
val MBS_HORZ_ZOOM_DEFAULT 0x00010000
//
bits horzPhaseCtrl 00204
13:00 dtoOffset
24:16 multiplyBase
:25 multiplySign
s 30:28 quantShift
val MBS_HORZ_PHASE_DEFAULT 0x11000c00
//
S26 horzZoomDelta 00208
val MBS_ZOOM_DELTA_DEFAULT 0
S29 horzZoomChange 0020c
val MBS_ZOOM_CHANGE_DEFAULT 0
//
// color space convertion coefficients
//
val MBS_REGOFFSET_CSM 0x220
bits csmCoeff0 00220
s 09:00 c00
s 19:10 c01
s 29:20 c02
val MBS_COEFF0_DEFAULT 0x0200
//
bits csmCoeff1 00224
s 09:00 c10
s 19:10 c11
s 29:20 c12
val MBS_COEFF1_DEFAULT 0x0800000
//
bits csmCoeff2 00228
s 09:00 c20
s 19:10 c21
s 29:20 c22
val MBS_COEFF2_DEFAULT 0x20000000
//
bits csmInputOffsets 0022c
07:00 d0
:08 d0Type // 0:unsigned, 1:signed
17:10 d1
:18 d1Type // 0:unsigned, 1:signed
27:20 d2
:28 d2Type // 0:unsigned, 1:signed
val MBS_INPUT_OFFSETS_DEFAULT 0x10040100
//
bits csmOutputOffsets 00230
s 09:00 e0
s 19:10 e1
s 29:20 e2
val MBS_OUTPUT_OFFSETS_DEFAULT 0
//
val MBS_REGOFFSET_VERT_ZOOM 0x240
bits vertInitialZoom 00240
19:00 scaleFactor
val MBS_VSP_SCALE_UNITY 0x10000
27:26 components
val MBS_VSP_2_COMP 0 // 2 component scaling
val MBS_VSP_3_COMP 2 // 3 component scaling
val MBS_VSP_4_COMP 3 // 4 component scaling
val MBS_VERT_ZOOM_DEFAULT 0x010000
31:29 phaseMode
//
union _vertPhaseCtrl { 00244
bits v0 00244
12:00 dtoOffset
20:16 chromaOffset
s 23:21 lineDiff
:25 multiplySign
s 30:28 quantShift
bits v1 00244
13:00 dtoOffset
19:14 chromaOffset
s 24:21 lineDiff
:25 multiplySign
s 30:28 quantShift
} vertPhaseCtrl;
val MBS_VERT_PHASE_DEFAULT 0x12000c00
//
S26 vertZoomDelta 00248
S29 vertZoomChange 0024c
//
val MBS_REGOFFSET_EDDI 0x260
bits eddiCtrl1 00260
:00 enable
03:01 minEdgeWidth
08:04 maxEdgeWidth
15:09 filterThreshold
21:16 minLumaDif
23:22 absEdgeWidthDif
27:24 edgeWidthScale // 0 - 15
val MBS_EDDI_CONTROL1_DEFAULT 0x0A9E0DE5 // enabled
bits eddiCtrl2 00264
:00 rcCheckEn
08:04 searchLimit
11:10 absRcmDif
15:12 rcmScale
val MBS_EDDI_CONTROL2_DEFAULT 0x0000A981
//
val MBS_REGOFFSET_MSA3_CTRL 0x270
bits msa3dynamicCtrl 00270
02:00 t1 // start of slope [0:7]
06:04 t2 // steepness of slope [0:7]
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