tmbslsaa7104local.h

PNX1500上7104芯片设置源代码！标准的C代码。

/*  Copyright (C) 2004 Koninklijke Philips Electronics N.V.
    All Rights Reserved. 
    This source code and any compilation or derivative thereof is the 
    proprietary information of Koninklijke Philips Electronics N.V. and is
    confidential in nature. 
    Under no circumstances is this software to be exposed to or placed under an
    Open Source License of any type without the expressed written permission of
    Koninklijke Philips Electronics N.V.
*//*
--------------------------------------------------------------------------------
    %name:         tmbslsaa7104local.h %
    %version:      ds08#12.1.3 %
    %date_created: Mon Oct 30 14:25:18 2006 %
--------------------------------------------------------------------------------
*/

/**
    @file   tmbslsaa7104local.h
    @brief  bsp driver for the SAA7104 video encoder.

@b  Component:  tmbsl7104.

    his source file contains the implementation 
    for the SAA7104 video output chip.

    Its interface is designed according to the definition of the 
    board support library.
*/

/******************************************************************************
* STANDARD INCLUDE FILES                                                      *
*******************************************************************************/

/******************************************************************************
* PROJECT INCLUDE FILES                                                       *
*******************************************************************************/

#include "tmbsl7104.h"
#include "tmVideoMode.h"

#ifndef TMBSL_7104_LOCAL_H
#define TMBSL_7104_LOCAL_H

#ifdef __cplusplus
extern "C"
{
#endif

/******************************************************************************
* LOCAL MACROS             					                                  *
*******************************************************************************/

#define saa7104_NREGS   0xfd    /* number of 7104 registers     */
#define saa7104_STARADR 0x00    /* Start for sub-addresses for 7125 */

#define saa7104_BLACKLEVEL_REG    0x5D    /* bits 0-5 */
#define FREQ  25.175e06L

// Max number of data bytes to be sent in one transfer
#define MAX_IIC_DATA_SIZE       80

#define saa7104_CONST_ANC 0x0000ffff
#define saa7104_DID 0x11
#define saa7104_SDID 0x11

#define VMUX_CTRL_10BIT         0x80    // vMuxCtrl 10-bit select bit on RevB
#define VMUX_CTRL_10BIT_REVA    0x40    //     10-bit select on RevA chip
#define VMUX_CTRL_QUALINVERT    0x80
#define IOPORT_CTRL_QUALINVERT  0x40
#define IOPORT_CTRL_SD_MODE     0x08    //  set for SD mode data path
#define IOPORT_CTRL_INVERT_MSBS 0x07    //  invert MSB on all 3 channels for 
                                        //  HD modes
#define MISC_CTRL_24BIT         0x40    //  set for 24-bit mode
#define MISC_CTRL_30BIT         0x00    //  set for 30-bit mode

#define DAC_CTRL_YUV            0xE0    //  set DACs for YUV
#define DAC_CTRL_CVBSEN         0x40    //  enable CVBS

#define SYNC_DELAY_VBIPROG      0x80    //  enable programming via VBI

#define PIX_TRANS		( 0x2 )
#define PIX1_TRANS		( PIX_TRANS )
#define PIX2_TRANS		( PIX_TRANS << 2 )
#define PIX3_TRANS		( PIX_TRANS << 4 )
#define PIX4_TRANS		( PIX_TRANS << 6 )


/******************************************************************************
* LOCAL TYPEDEFS     														  *
*******************************************************************************/
	
typedef enum
{
    saa7104Rev5    = 1
	
} tmbslsaa7104Rev_t;

typedef struct subaddInfo_t 
{
    UInt8       subAddr;        // Subaddress of saa7104 register
    UInt8       value;          // Data for this register
} subaddInfo_t;

#if 0
typedef struct saa7104L21Info{
    UInt8       odd0Byte;        
    UInt8       even0Byte;       
    UInt8       odd1Byte;        
    UInt8       even1Byte;       
} saa7104L21Info_t;

typedef struct saa7104WSSInfo{
    UInt32       aspectRatio : 4;        
    UInt32       enhancedServices : 4;
    UInt32       subtitles : 4;        
} saa7104WSSInfo_t;

typedef struct saa7104VPSInfo{
    UInt8 vpsByte5;
    UInt8 vpsByte11;
    UInt8 vpsByte12;
    UInt8 vpsByte13;
    UInt8 vpsByte14;

} saa7104WSSInfo_t;
#endif

typedef enum
{
    vMuxCtrlYuv422,
    vMuxCtrl444,
    vMuxCtrl444x,
    vMuxCtrlYuvHd,          // double interface mode
    vMuxCtrlYuvHd422        // single interface mode (not avail on RevA)
} vMuxCtrlInterfaceMode_t;

typedef enum 
{
	pcl_1		= 0x81,
	pcl_2		= 0x82,
	pcl_3		= 0x83,
	
	hdline_0	= 0xD0,
	hdline_1	= 0xD1,
	hdline_2	= 0xD2,
	hdline_3	= 0xD3,
	hdline_4	= 0xD4,
	hdline_8	= 0xD8,
	hdctrl		= 0xDC,
	
	cursa		= 0xFE	
} saa7104_Reg_t;

typedef struct saa7104_HDSync
{
	ConstString		videoStd;
	
	UInt32			d0Sz;
	const UInt8		*pD0;
	UInt32			d1Sz;
	const UInt8		*pD1;
	UInt32			d2Sz;
	const UInt8		*pD2;
	UInt32			d3Sz;
	const UInt8		*pD3;
	
	const UInt8		*pD4;
	const UInt8		*pD8;
	
} saa7104_HDSync_t, *psaa7104_HDSync_t;

/******************************************************************************
* STATIC DATA                  												  *
*******************************************************************************/

/* saa7104 regs */
static const subaddInfo_t saa7104_init[] = 
{
	{0x01 , 0x00},  // Null
    {0x02 , 0x00},  // Null
    {0x03 , 0x00},  // Null
    {0x04 , 0x00},  // Null
    {0x05 , 0x00},  // Null
    {0x06 , 0x00},  // Null
    {0x07 , 0x00},  // Null
    {0x08 , 0x00},  // Null
    {0x09 , 0x00},  // Null
    {0x0a , 0x00},  // Null
    {0x0b , 0x00},  // Null
    {0x0c , 0x00},  // Null
    {0x0d , 0x00},  // Null
    {0x0e , 0x00},  // Null
    {0x0f , 0x00},  // Null
    {0x10 , 0x00},  // Null
    {0x11 , 0x00},  // Null
    {0x12 , 0x00},  // Null
    {0x13 , 0x00},  // Null
    {0x14 , 0x00},  // Null
    {0x15 , 0x00},  // Null
    {0x16 , 0x06},  // Common DAC adjust fine
    {0x17 , 0x1b},	// R DAC adjust coarse
    {0x18 , 0x1b},	// G DAC adjust coarse
    {0x19 , 0x1f},	// B DAC adjust coarse
    {0x1a , 0x20},	// monitor sense threshold
    {0x1b , 0x27},	// monitor sense mode
    {0x1d , 0x00},  // ??
    {0x1e , 0x00},  // ??
    {0x1f , 0x00},  // ??
    {0x20 , 0x00},  // ??
    {0x21 , 0x00},  // ??
    {0x24 , 0x00},  // ??
    {0x25 , 0x00},  // ??
    {0x26 , 0xff},  // Wide screen signal
    {0x27 , 0x3f},  // Wide screen signal
    {0x28 , 0x19},  // Real-time control, burst start
    {0x29 , 0x1d},  // Sync reset enable, burst end
    {0x2a , 0xff},  // Copy generation 0
    {0x2b , 0xff},  // Copy generation 1
    {0x2c , 0x0f},  // CG enable, copy generation 2
    {0x2d , 0xb0},  // Output port control
    {0x2e , 0x00},  // Null
    {0x2f , 0x00},  // Null
    {0x30 , 0x00},  // Null
    {0x31 , 0x00},  // Null
    {0x32 , 0x00},  // Null
    {0x33 , 0x00},  // Null
    {0x34 , 0x00},  // Null
    {0x35 , 0x00},  // Null
    {0x36 , 0x00},  // Null
    {0x37 , 0x00},	// Input path control
    {0x38 , 0x00},	// Gain luminance for RGB
    {0x39 , 0x00},	// Gain colour difference for RGB
    {0x3a , 0x39},	// Input port control 1
    {0x54 , 0x12},  // VPS enable, input control 2
    {0x55 , 0x0f},  // VPS byte 5
    {0x56 , 0xc3},  // VPS byte 11
    {0x57 , 0x00},  // VPS byte 12
    {0x58 , 0x02},  // VPS byte 13
    {0x59 , 0x30},  // VPS byte 14
    {0x5a , 0x27},  // Chrominance phase
    {0x5b , 0x7b},  // Gain U
    {0x5c , 0xb1},  // Gain V
    {0x5d , 0x3a},  // Gain U MSB, black level
    {0x5e , 0x2e},  // Gain V MSB, blanking level
    {0x5f , 0x2e},  // cross color, blanking level VBI
    {0x60 , 0x00},  // Null
    {0x61 , 0x15},  // Standard control
    {0x62 , 0x3f},  // Burst amplitude
    {0x63 , 0x1f},  // Subcarrier 0
    {0x64 , 0x7c},  // Subcarrier 1
    {0x65 , 0xf0},  // Subcarrier 2
    {0x66 , 0x21},  // Subcarrier 3
    {0x67 , 0x00},  // Line 21 odd 0
    {0x68 , 0x00},  // Line 21 odd 1
    {0x69 , 0x00},  // Line 21 even 0
    {0x6a , 0x00},  // Line 21 even 1
    {0x6c , 0x00},  // Trigger control
    {0x6d , 0x00},  // Trigger control
    {0x6e , 0x90},  // Multi control
    {0x6f , 0x06},  // Closed Caption, teletext enable
    {0x70 , 0xff},  // Active display window horizontal start
    {0x71 , 0x9f},  // Active display window horizontal end
    {0x72 , 0x60},  // MSBs ADWH
    {0x73 , 0x90},  // TTX request horizontal start
    {0x74 , 0x04},  // TTX request horizontal delay
    {0x75 , 0xb0},  // CSYNC advance
    {0x76 , 0x78},  // TTX odd request vertical start
    {0x77 , 0xf9},  // TTX odd request vertical end
    {0x78 , 0x2a},  // TTX even request vertical start
    {0x79 , 0xfa},  // TTX even request vertical end
    {0x7a , 0x13},  // First active line
    {0x7b , 0x05},  // Last active line
    {0x7c , 0x40},  // TTX mode, MSB vertical
    {0x7d , 0x00},  // Null
    {0x7e , 0x00},  // Disable TTX line
    {0x7f , 0x00},  // Disable TTX line
    {0x81 , 0x00},  // Pixel clock 0
    {0x82 , 0x00},  // Pixel clock 1
    {0x83 , 0x00},  // Pixel clock 2
    {0x84 , 0xf5},  // Pixel clock control
    {0x85 , 0x08},  // FIFO control
    {0x90 , 0x03},  // Horizontal offset
    {0x91 , 0xd0},  // Pixel number
    {0x92 , 0x12},  // Vertical offset odd
    {0x93 , 0x12},  // Vertical offset even
    {0x94 , 0x08},  // MSBs
    {0x95 , 0xf0},  // Line number
    {0x96 , 0x30},  // Scaler CTRL, MCB YPIX
    {0x97 , 0x15},  // Sync control
    {0x98 , 0xb3},  // Line length
    {0x99 , 0x06},  // Input delay, MSB line length
    {0x9a , 0x00},  // Horizontal increment
    {0x9b , 0x00},  // Vertical increment
    {0x9c , 0x08},  // MSBs vertical and horizontal increment
    {0x9d , 0x64},  // Weighting factor odd
    {0x9e , 0x64},  // Weighting factor even
    {0x9f , 0x00},  // Weighting factor MSB
    {0xa0 , 0x00},  // Vertical line skip
    {0xa1 , 0x00},  // Blank enable for NI-bypass, vertical line skip MSB
    {0xa2 , 0x10},  // Border colour Y
    {0xa3 , 0x80},  // Border colour U
    {0xa4 , 0x80},  // Border colour V
    /* d0 to d7 programmed later if HD sync gen is used */
    {0xdc , 0x00},	// HD output control
    {0xf0 , 0xff},  // Cursor colour 1 R
    {0xf1 , 0xff},  // Cursor colour 1 G
    {0xf2 , 0xff},  // Cursor colour 1 B
    {0xf3 , 0x00},  // Cursor colour 2 R
    {0xf4 , 0x00},  // Cursor colour 2 G
    {0xf5 , 0x00},  // Cursor colour 2 B
    {0xf6 , 0x00},  // Auxiliary cursor colour R
    {0xf7 , 0x00},  // Auxiliary cursor colour G
    {0xf8 , 0xff},  // Auxiliary cursor colour B
    {0xf9 , 0xf8},  // Horizontal cursor position  // put cursor to outter side for 1080i (TaMa)
    {0xfa , 0x07},  // Horizontal hot spot, MSB XCP
    {0xfb , 0x34},  // Vertical cursor position
    {0xfc , 0x00},  // Vertical hot spot, MSB YCP
    {0xfd , 0xd3}   // Cursor control
};



static const subaddInfo_t saa7104_pal[] = {
    {0x28, 0x21},        /* BS */
    {0x29, 0x1d},        /* BE */

    {0x5B, 0x7D},        /* Gain-U */
    {0x5C, 0xAF},        /* Gain-V */
    {0x5D, 0x2D},        /* Gain-U MSB, Black Level */
    {0x5E, 0x3F},        /* Gain-V MSB, Blanking Level */
    {0x5F, 0x3F},        /* Gain-V MSB, Blanking Level in Vertical */

    {0x61, 0x16},        /* Standard Control */
    {0x62, 0x2d},        /* Burst Amplitude */

    {0x63, 0xcb},        /* Subcarrier Frequency, Byte 0 */
    {0x64, 0x8a},        /* Subcarrier Frequency, Byte 1 */
    {0x65, 0x09},        /* Subcarrier Frequency, Byte 2 */
    {0x66, 0x2a},        /* Subcarrier Frequency, Byte 3 */

    {0x6E, 0x80},        /* Reset when changing Subcarrier frequency */

    {0x70, 0x19},		 // Active display window start
    {0x71, 0xb9},		 // Active display window end
    {0x72, 0x61},		 // Active display window MSB start/end
    
    {0x7A, 0x17},        /* First Active Line don't care if 0x6E is 0x80 */
    {0x7B, 0x36},        /* Last Active Line  don't care if 0x6E is 0x80 */
    {0x7C, 0x40},        /* (MSB's),          don't care if 0x6E is 0x80 */

    {0x90, 0x03},        
    {0x92, 0x16},
    {0x93, 0x16},

	{0x98, 0xbf},   	//HLEN lsbs
	{0x99, 0x06},   	//HLEN msbs
	{0x95, 0x20},   	//VLEN lsbs
	{0x96, 0x31}   		//VLEN msbs
};


static const subaddInfo_t saa7104_ntsc[] = {
    {0x28, 0x19},        /* BS */
    {0x29, 0x1d},        /* BE */
//    {0x3A, 0x39},        /* Input port control */
    
    {0x5A, 0x27},        /* CHPS */    
    {0x5B, 0x7b},        /* Gain-U */
    {0x5C, 0xb1},        /* Gain-V */
    {0x5D, 0x3a},        /* Gain-U MSB, Black Level */
    {0x5E, 0x2e},        /* Gain-V MSB, Blanking Level */
    {0x5F, 0x2e},        /* Gain-V MSB, Blanking Level in Vertical */