cfw.c

2440开发板

    } while  (liBase.LowPart != CurTicks.LowPart) ;  

    lpliPerformanceCount->QuadPart = liBase.QuadPart + dwCurCount;
    
    return TRUE;
}



//------------------------------------------------------------------------------
//
//  OEMQueryPerformanceFrequency
//  
//      The OEMQueryPerformanceFrequency function retrieves the frequency of 
//      the high-resolution performance counter, if one exists. 
//  
//  BOOL OEMQueryPerformanceFrequency(
//  
//      LARGE_INTEGER  *lpliPerformanceFreq     // address of current frequency
//     );   
//  
//  Parameters
//  
//  lpliPerformanceFreq
//  
//      Points to a variable that the function sets, in counts per second, to 
//      the current performance-counter frequency. If the installed hardware 
//      does not support a high-resolution performance counter, this parameter
//      can be to zero. 
//  
//  Return Value
//  
//      If the installed hardware supports a high-resolution performance 
//      counter, the return value is TRUE.
//      If the installed hardware does not support a high-resolution 
//      performance counter, the return value is FALSE.
//  
//  If this function is implemented by the OEM, the pointer pQueryPerformanceFrequency
//  should be initialized as follows:
//  
//  BOOL (*pQueryPerformanceFrequency)(LARGE_INTEGER *lpPerformanceFrequency)=OEMQueryPerformanceFrequency;
//
//------------------------------------------------------------------------------
BOOL 
OEMQueryPerformanceFrequency(
    LARGE_INTEGER *lpliPerformanceFreq
    ) 
{
    extern DWORD PerfCountFreq();
    
    lpliPerformanceFreq->HighPart = 0;
    lpliPerformanceFreq->LowPart  = PerfCountFreq();
    return TRUE;
}

// set pointers to OEM functions
BOOL (*pQueryPerformanceCounter)(LARGE_INTEGER *lpliPerformanceCount)=OEMQueryPerformanceCounter;
BOOL (*pQueryPerformanceFrequency)(LARGE_INTEGER *lpliPerformanceFreq)=OEMQueryPerformanceFrequency;


//
// CPU-specific functions for OEMIdle
//
extern void  CPUEnterIdle(DWORD dwIdleParam);
extern DWORD CPUGetSysTimerCountMax(DWORD dwIdleMSecRequested);
extern void  CPUSetSysTimerCount(DWORD dwIdleMSec);
extern BOOL CPUClearSysTimerIRQ(void);


//
// dougfir or later
//
extern DWORD
CPUGetSysTimerCountElapsed(
    DWORD dwTimerCountdownMSec,
    volatile DWORD *pCurMSec,
    DWORD *pPartialCurMSec,
    volatile ULARGE_INTEGER *pCurTicks
    );

//------------------------------------------------------------------------------
//
//  This routine is called by the kernel when there are no threads ready to
//  run. The CPU should be put into a reduced power mode and halted. It is 
//  important to be able to resume execution quickly upon receiving an interrupt.
//  Note: It is assumed that interrupts are off when OEMIdle is called.  Interrrupts
//  are turned off when OEMIdle returns.
//
//------------------------------------------------------------------------------
static DWORD dwPartialCurMSec = 0;		// Keep CPU-specific sub-millisecond leftover.
void
OEMIdle( DWORD dwIdleParam )
{
	DWORD dwIdleMSec;
	DWORD dwPrevMSec = *pCurMSec;

	// Use for 64-bit math
	ULARGE_INTEGER currIdle = { curridlelow, curridlehigh };

	if ((int) (dwIdleMSec = dwReschedTime - dwPrevMSec) <= 0) 
	{
		return;				// already time to wakeup
	}

	// just idle till tick if profiling or running iltiming
	if (bProfileTimerRunning || fIntrTime)	// fIntrTime : Interrupt Latency timeing.
	{
		// idle till end of 'tick'
		CPUEnterIdle(dwIdleParam);

		// Update global idle time and return
		currIdle.QuadPart += RESCHED_PERIOD;
		curridlelow = currIdle.LowPart;
		curridlehigh = currIdle.HighPart;
        
		return;
	}

	//
	// Since OEMIdle( ) is being called in the middle of a normal reschedule
	// period, CurMSec, dwPartialCurMSec, and CurTicks need to be updated accordingly.
	// Once we reach this point, we must re-program the timer (if we ever did) 
	// because dwPartialCurMSec will be modified in the next function call.
	//
	CPUGetSysTimerCountElapsed(RESCHED_PERIOD, pCurMSec, &dwPartialCurMSec, pCurTicks);

	if ((int) (dwIdleMSec -= *pCurMSec - dwPrevMSec) > 0)
	{
		dwPrevMSec = *pCurMSec;

		//
		// The system timer may not be capable of arbitrary timeouts. Get the
		// CPU-specific highest possible timeout available.
		//
		dwIdleMSec = CPUGetSysTimerCountMax(dwIdleMSec);

		//
		// Set the timer to wake up much later than usual, if needed.
		//
		CPUSetSysTimerCount(dwIdleMSec);
		CPUClearSysTimerIRQ( );

		//
		// Enable wakeup on any interrupt, then go to sleep.
		//
//		DEBUGMSG(1, (TEXT("OEMIDle  \r\n")));
		CPUEnterIdle(dwIdleParam);
		INTERRUPTS_OFF( );
        
		//
		// We're awake! The wake-up ISR (or any other ISR) has already run.
		//
		if (dwPrevMSec != *pCurMSec)
		{
			//
			// We completed the full period we asked to sleep.  Update the counters.
			//
			*pCurMSec  += (dwIdleMSec - RESCHED_PERIOD); // Subtract resched period, because ISR also incremented.
			CurTicks.QuadPart += (dwIdleMSec - RESCHED_PERIOD) * dwReschedIncrement;

			currIdle.QuadPart += dwIdleMSec;
		} else {
			//
			// Some other interrupt woke us up before the full idle period was
			// complete.  Determine how much time has elapsed.
			//
			currIdle.QuadPart += CPUGetSysTimerCountElapsed(dwIdleMSec, pCurMSec, &dwPartialCurMSec, pCurTicks);
		}
	}

	// Re-arm counters
	CPUSetSysTimerCount(RESCHED_PERIOD);
	CPUClearSysTimerIRQ( );

	// Update global idle time
	curridlelow = currIdle.LowPart;
	curridlehigh = currIdle.HighPart;

	return;
}

//------------------------------------------------------------------------------
//
//  DWORD GetTickCount(VOID)    Return count of time since boot in milliseconds
//
//------------------------------------------------------------------------------
DWORD 
SC_GetTickCount(void) 
{
	DWORD dwInc = 0, dwPartial = dwPartialCurMSec;
	DWORD curReturnMSec;
	ULARGE_INTEGER cdummy = {0, 0};

	curReturnMSec=*pCurMSec;
	CPUGetSysTimerCountElapsed(RESCHED_PERIOD, &dwInc, &dwPartial, &cdummy);

	return (curReturnMSec==*pCurMSec)?curReturnMSec+dwInc:*pCurMSec;
}


volatile BOOL fResumeFlag;
extern void CPUEnterIdleMode(void);

//------------------------------------------------------------------------------
// Initialize SDMMC block.. 
//------------------------------------------------------------------------------
static void InitSDMMC(void) 
{
	volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;

	// Initialize SDMMC and Configure SDMMC Card Detect
	// GPIO Configure 
	// RETAILMSG(1,(TEXT("SDMMC config current rGPGCON: %x\r\n"), s2440IOP->rGPGCON));  
	// We must need this PULL-UP routines to inialize.
	// s2440IOP->rGPGUP = 0xF800;   
#if SDIO_FOR_100BD		// for b'd revision 1.00
	// s2440IOP->rGPGUP &= ~(1<<10);
	s2440IOP->rGPGUP = 0xF800;
	s2440IOP->rGPGCON &= ~((0x3 << 20));   
	s2440IOP->rGPGCON |=  ((0x2 << 20));			// External Interrupt #18 Enable
	RETAILMSG(1,(TEXT("SDMMC config set rGPGCON: %x\r\n"), s2440IOP->rGPGCON));   
	s2440IOP->rEXTINT2 &= ~(0x7 << 8);			// Configure EINT18 as Both Edge Mode
	s2440IOP->rEXTINT2 |=  (0x3 << 8);
#else						// for b'd revision 0.17
	s2440IOP->rGPGUP = 0xF800;   
	s2440IOP->rGPGCON &= ~((0x3 << 16));   
	s2440IOP->rGPGCON |=  ((0x2 << 16));		/* External Interrupt #16 Enable				*/
	RETAILMSG(1,(TEXT("SDMMC config set rGPGCON: %x\r\n"), s2440IOP->rGPGCON));   
	s2440IOP->rEXTINT2 &= ~(0x7 << 0);			/* Configure EINT16 as Both Edge Mode		*/
	s2440IOP->rEXTINT2 |=  (0x0 << 0);			// low level trig
#endif
	/* Configure SDMMC Write Protect */
	s2440IOP->rGPHUP = 0x0;   
	s2440IOP->rGPHCON &= ~((0x3 << 16));   
	s2440IOP->rGPHCON |=  ((0x0 << 16));		/* GPH8/UCLK Write Protect Pin	*/
	s2440IOP->rGPGCON &= ~(3 << 20);
	s2440IOP->rGPGCON |= (2 << 20);
	s2440IOP->rGPECON &= ~(0xfff << 10);
	s2440IOP->rGPECON |= (0xaaa << 10);	
	//			RETAILMSG(1, (TEXT("rGPGCON = 0x%x, s2440IOP->rGPGCON\r\n")));
	//		RETAILMSG(1, (TEXT("rGPECON = 0x%x, s2440IOP->rGPECON\r\n")));

	RETAILMSG(1,(TEXT("SDMMC config Init Done.\r\n")));   
}

//------------------------------------------------------------------------------
// Initialize and test the LCD block.. 
//------------------------------------------------------------------------------

/*
// Define some values for TFT 16bpp
#if(LCDTYPE == TFT16BPP)    // TFT 640*480 / 16bpp
#define FR_WIDTH            240
#define FR_HEIGHT           320
#define PhysicalVmemSize    FR_HEIGHT*FR_WIDTH*LCDTYPE


struct FrameBuffer {
   unsigned short pixel[FR_HEIGHT][FR_WIDTH];
};

#else if(LCDTYPE == STN8BPP)// STN 320*240 / 8bpp
#define FR_WIDTH            320
#define FR_HEIGHT           240
#define PhysicalVmemSize    FR_HEIGHT*FR_WIDTH

struct FrameBuffer {
   unsigned char pixel[FR_HEIGHT][FR_WIDTH];
};
#endif
*/

#if (LCD_TYPE == TFT6400_480)
struct FrameBuffer {
	unsigned short pixel[LCD_YSIZE_TFT][LCD_XSIZE_TFT];
};
struct FrameBuffer *FBuf;
#elif (LCD_TYPE == TFT320_240)
struct FrameBuffer *FBuf;
#endif

static void InitDisplay()
{
	int i, j;
	volatile IOPreg *s2440IOP;
	volatile LCDreg *s2440LCD;    

	s2440IOP = (IOPreg *)IOP_BASE;
	s2440LCD = (LCDreg *)LCD_BASE; 

//	LCD port initialize.
	s2440IOP->rGPCUP  = 0xFFFFFFFF;
	s2440IOP->rGPCCON = 0xAAAAAAAA;

	s2440IOP->rGPDUP  = 0xFFFFFFFF;
	s2440IOP->rGPDCON = 0xAAAAAAAA;

	s2440IOP->rGPGCON &= ~(3 << 8);					// Set LCD_PWREN as output
	s2440IOP->rGPGCON |=  (1 << 8);

	s2440IOP->rGPGDAT |=  (1 << 4);					// Backlight ON

#if (LCD_TYPE == TFT640_480)

	s2440LCD->rLCDCON1   =  (1 << 8) |		// VCLK = HCLK / ((CLKVAL + 1) * 2) -> About 7 Mhz  // ;;; SHL
							(0 << 7) |		// 0 : Each Frame
							(3 << 5) |		// TFT LCD Pannel
							(12<< 1) |		// 16bpp Mode
							(0 << 0) ;		// Disable LCD Output

	s2440LCD->rLCDCON2   =  (VBPD        << 24) |	// VBPD          :   1
							(LINEVAL_TFT << 14) |	// Virtical Size : 320 - 1
							(VFPD        <<  6) |	// VFPD          :   2
							(VSPW        <<  0) ;	// VSPW          :   1

	s2440LCD->rLCDCON3   =  (HBPD        << 19) |	// HBPD          :   6
							(HOZVAL_TFT  <<  8) |	// HOZVAL_TFT    : 240 - 1
							(HFPD        <<  0) ;	// HFPD          :   2


	s2440LCD->rLCDCON4   =  (MVAL        <<  8) |	// MVAL          :  13                              */
							(HSPW        <<  0) ;	// HSPW          :   4                              */

	s2440LCD->rLCDCON5   =  (0 << 12) |		// BPP24BL       : LSB valid
							(1 << 11) |		// FRM565 MODE   : 5:6:5 Format
							(0 << 10) |		// INVVCLK       : VCLK Falling Edge
							(0 <<  9) |		// INVVLINE      : Inverted Polarity
							(0 <<  8) |		// INVVFRAME     : Inverted Polarity
							(0 <<  7) |		// INVVD         : Normal
							(0 <<  6) |		// INVVDEN       : Normal
							(0 <<  5) |		// INVPWREN      : Normal
							(0 <<  4) |		// INVENDLINE    : Normal
							(0 <<  3) |		// PWREN         : Disable PWREN
							(0 <<  2) |		// ENLEND        : Disable LEND signal
							(0 <<  1) |		// BSWP          : Swap Disable
							(1 <<  0) ;		// HWSWP         : Swap Enable

	s2440LCD->rLCDSADDR1 = ((FRAMEBUF_DMA_BASE >> 22) << 21) |
							((M5D(FRAMEBUF_DMA_BASE >> 1)) <<  0);

	s2440LCD->rLCDSADDR2 = M5D((FRAMEBUF_DMA_BASE + (LCD_XSIZE_TFT * LCD_YSIZE_TFT * 2)) >> 1);

	s2440LCD->rLCDSADDR3 = (((LCD_XSIZE_TFT - LCD_XSIZE_TFT) / 1) << 11) | (LCD_XSIZE_TFT / 1);

//	s2440LCD->rLPCSEL    |= 0x3;	// for aiji
	s2440LCD->rLCDINTMSK |= (3);
	s2440LCD->rTCONSEL   &= ~(0x7);	// ;;; SHL
	s2440LCD->rTPAL       = 0x0;
	s2440LCD->rTCONSEL   &= ~((1<<4) | 1);								// Disable LCC3600, LCP3600
	s2440IOP->rGPGUP	  = s2440IOP->rGPGUP  & (~(1<<4)) | (1<<4);		// Pull-up disbale
	s2440IOP->rGPGCON	  = s2440IOP->rGPGCON & (~(3<<8)) | (3<<8);
	s2440LCD->rLCDCON5    = s2440LCD->rLCDCON5 & (~(1<<3)) | (1<<3);	// PWREN
	s2440LCD->rLCDCON5    = s2440LCD->rLCDCON5 & (~(1<<5)) | (0<<5);	// INVPWREN
	s2440LCD->rLCDCON1	 |= 1;											// Enable LCD output

#elif (LCD_TYPE == TFT320_240)

    s2440LCD->rLCDCON1=(5<<8)|(MVAL_USED<<7)|(3<<5)|(12<<1)|0;
        // TFT LCD panel,16bpp TFT,ENVID=off
	s2440LCD->rLCDCON2=(VBPD<<24)|(LINEVAL_TFT<<14)|(VFPD<<6)|(VSPW);
	s2440LCD->rLCDCON3=(HBPD<<19)|(HOZVAL_TFT<<8)|(HFPD);
	s2440LCD->rLCDCON4=(MVAL<<8)|(HSPW);
	s2440LCD->rLCDCON5=(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<3)|(1<<0);////	//FRM5:6:5,HSYNC and VSYNC are inverted
	s2440LCD->rLCDSADDR1=((FRAMEBUF_DMA_BASE>>22)<<21)|M5D(FRAMEBUF_DMA_BASE>>1);
	s2440LCD->rLCDSADDR2=M5D( (FRAMEBUF_DMA_BASE+(LCD_XSIZE_TFT*LCD_YSIZE_TFT*2))>>1 );
	s2440LCD->rLCDSADDR3=(((LCD_XSIZE_TFT-LCD_XSIZE_TFT)/1)<<11)|(LCD_XSIZE_TFT/1);
	s2440LCD->rLCDINTMSK|=(3); // MASK LCD Sub Interrupt
//	s2440LCD->rTCONSEL   &= ~(0x7);	// ;;; SHL
//	s2440LCD->rTCONSEL   &= ~((1<<4) | 1);	
	s2440LCD->rTPAL=0; // Disable Temp Palette
	
	s2440LCD->rLCDCON1 |= 1;
	

#endif

#if (LCD_TYPE == TFT640_480)

	FBuf = (struct FrameBuffer *) (FRAMEBUF_BASE);

	// Test LCD display status with R.G.B and White color.
	for (i=0; i<LCD_YSIZE_TFT/2; i++)
	{
		for (j=0; j<LCD_XSIZE_TFT; j++)
		{
			if (j<LCD_XSIZE_TFT/2)
				#if (LCDTYPE == TFT16BPP)
					FBuf->pixel[i][j]=0xffff;
				#else
					FBuf->pixel[i][j]=0xff;
				#endif
			else
				#if (LCDTYPE == TFT16BPP)
					FBuf->pixel[i][j]=0xf800;
				#else
					FBuf->pixel[i][j]=0xe0;
				#endif
		}
	}

	for (i=LCD_YSIZE_TFT/2; i<LCD_YSIZE_TFT; i++)
	{
		for (j=0; j<LCD_XSIZE_TFT; j++)
		{
			if (j<LCD_XSIZE_TFT/2)
				#if (LCDTYPE == TFT16BPP)
					FBuf->pixel[i][j]=0x07e0;
				#else
					FBuf->pixel[i][j]=0x1c;
				#endif
			else
				#if (LCDTYPE == TFT16BPP)
					FBuf->pixel[i][j]=0x001f;
				#else
					FBuf->pixel[i][j]=0x03;
				#endif
		}
	}

#elif (LCD_TYPE == TFT320_240)
	memcpy((void *)FRAMEBUF_BASE, ScreenBitmap, ARRAY_SIZE_TFT_16BIT);
//    rle_express(ScreenBitmap, (unsigned short *)FRAMEBUF_BASE, 0x8a8c / 2);
#endif
}

static void OEMInitInterrupts(void)	// for KITL 030828
{
	volatile INTreg *s2440INT = (INTreg *)INT_BASE;
	volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;

	// Configure EINT9 for CS8900 interrupt.
	//
	s2440IOP->rGPGCON  = (s2440IOP->rGPGCON  & ~(0x3 << 0x2)) | (0x2 << 0x2);		// GPG1 == EINT9.
	s2440IOP->rGPGUP   = (s2440IOP->rGPGUP   |  (0x1 << 0x1));						// Disable pull-up.
	s2440IOP->rEXTINT1 = (s2440IOP->rEXTINT1 & ~(0xf << 0x4)) | (0x1 << 0x4);		// Level-high triggered.

	// Configure EINT8 for PD6710 interrupt.
	//
	s2440IOP->rGPGCON  = (s2440IOP->rGPGCON  & ~(0x3 << 0x0)) | (0x2 << 0x0);		// GPG0 == EINT8.
	s2440IOP->rGPGUP   = (s2440IOP->rGPGUP   |  (0x1 << 0x0));						// Disable pull-up.
	s2440IOP->rEXTINT1 = (s2440IOP->rEXTINT1 & ~(0xf << 0x0)) | (0x1 << 0x0);		// Level-high triggered.

	// Mask and clear all peripheral interrupts (these come through a second-level "GPIO" interrupt register).
	//
	s2440IOP->rEINTMASK = BIT_ALLMSK;	// Mask all EINT interrupts.
	s2440IOP->rEINTPEND = BIT_ALLMSK;	// Clear pending EINT interrupts.

	// Mask and clear all interrupts.
	//
	s2440INT->rINTMSK = BIT_ALLMSK;			// Mask all interrupts (reset value).
	s2440INT->rINTMSK &= ~BIT_BAT_FLT;
	s2440INT->rSRCPND = BIT_ALLMSK;			// Clear pending interrupts.
	s2440INT->rINTPND = s2440INT->rINTPND;		// S3C2440X developer notice (page 4) warns against writing a 1 to any
							// 0 bit field in the INTPND register.  Instead we'll write the INTPND value itself.
}