📄 at91sam9263_inc.h
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#define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority#define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority// -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- #define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority// -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- // -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- // -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- // -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- // -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- // -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- // -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- // -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- // -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register -------- // -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register -------- // -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register -------- // -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register -------- // -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register -------- // -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register -------- // -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- #define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data#define AT91C_MATRIX_RCB2 (0x1 << 2) // (MATRIX) Remap Command Bit for PDC#define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for LCD#define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for 2DGC#define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for ISI#define AT91C_MATRIX_RCB6 (0x1 << 6) // (MATRIX) Remap Command Bit for DMA#define AT91C_MATRIX_RCB7 (0x1 << 7) // (MATRIX) Remap Command Bit for EMAC#define AT91C_MATRIX_RCB8 (0x1 << 8) // (MATRIX) Remap Command Bit for USB// *****************************************************************************// SOFTWARE API DEFINITION FOR AHB CCFG Interface// *****************************************************************************// *** Register offset in AT91S_CCFG structure ***#define CCFG_TCMR ( 4) // TCM configuration#define CCFG_EBI0CSA (16) // EBI0 Chip Select Assignement Register#define CCFG_EBI1CSA (20) // EBI1 Chip Select Assignement Register#define CCFG_MATRIXVERSION (236) // Version Register// -------- CCFG_TCMR : (CCFG Offset: 0x4) TCM Configuration -------- #define AT91C_CCFG_ITCM_SIZE (0xF << 0) // (CCFG) Size of ITCM enabled memory block#define AT91C_CCFG_ITCM_SIZE_0KB (0x0) // (CCFG) 0 KB (No ITCM Memory)#define AT91C_CCFG_ITCM_SIZE_16KB (0x5) // (CCFG) 16 KB#define AT91C_CCFG_ITCM_SIZE_32KB (0x6) // (CCFG) 32 KB#define AT91C_CCFG_DTCM_SIZE (0xF << 4) // (CCFG) Size of DTCM enabled memory block#define AT91C_CCFG_DTCM_SIZE_0KB (0x0 << 4) // (CCFG) 0 KB (No DTCM Memory)#define AT91C_CCFG_DTCM_SIZE_16KB (0x5 << 4) // (CCFG) 16 KB#define AT91C_CCFG_DTCM_SIZE_32KB (0x6 << 4) // (CCFG) 32 KB#define AT91C_CCFG_RM (0xF << 8) // (CCFG) Read Margin registers// -------- CCFG_EBI0CSA : (CCFG Offset: 0x10) EBI0 Chip Select Assignement Register -------- #define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller.#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller.#define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.#define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.#define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.#define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.#define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment#define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC#define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.#define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration// -------- CCFG_EBI1CSA : (CCFG Offset: 0x14) EBI1 Chip Select Assignement Register -------- #define AT91C_EBI_CS2A (0x1 << 3) // (CCFG) EBI1 Chip Select 2 Assignment#define AT91C_EBI_CS2A_SMC (0x0 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller.#define AT91C_EBI_CS2A_SM (0x1 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.// *****************************************************************************// SOFTWARE API DEFINITION FOR Peripheral DMA Controller// *****************************************************************************// *** Register offset in AT91S_PDC structure ***#define PDC_RPR ( 0) // Receive Pointer Register#define PDC_RCR ( 4) // Receive Counter Register#define PDC_TPR ( 8) // Transmit Pointer Register#define PDC_TCR (12) // Transmit Counter Register#define PDC_RNPR (16) // Receive Next Pointer Register#define PDC_RNCR (20) // Receive Next Counter Register#define PDC_TNPR (24) // Transmit Next Pointer Register#define PDC_TNCR (28) // Transmit Next Counter Register#define PDC_PTCR (32) // PDC Transfer Control Register#define PDC_PTSR (36) // PDC Transfer Status Register// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // *****************************************************************************// SOFTWARE API DEFINITION FOR Debug Unit// *****************************************************************************// *** Register offset in AT91S_DBGU structure ***#define DBGU_CR ( 0) // Control Register#define DBGU_MR ( 4) // Mode Register#define DBGU_IER ( 8) // Interrupt Enable Register#define DBGU_IDR (12) // Interrupt Disable Register#define DBGU_IMR (16) // Interrupt Mask Register#define DBGU_CSR (20) // Channel Status Register#define DBGU_RHR (24) // Receiver Holding Register#define DBGU_THR (28) // Transmitter Holding Register#define DBGU_BRGR (32) // Baud Rate Generator Register#define DBGU_CIDR (64) // Chip ID Register#define DBGU_EXID (68) // Chip ID Extension Register#define DBGU_FNTR (72) // Force NTRST Register#define DBGU_RPR (256) // Receive Pointer Register#define DBGU_RCR (260) // Receive Counter Register#define DBGU_TPR (264) // Transmit Pointer Register#define DBGU_TCR (268) // Transmit Counter Register#define DBGU_RNPR (272) // Receive Next Pointer Register#define DBGU_RNCR (276) // Receive Next Counter Register#define DBGU_TNPR (280) // Transmit Next Pointer Register#define DBGU_TNCR (284) // Transmit Next Counter Register#define DBGU_PTCR (288) // PDC Transfer Control Register#define DBGU_PTSR (292) // PDC Transfer Status Register// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG// *****************************************************************************// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller// *****************************************************************************// *** Register offset in AT91S_AIC structure ***#define AIC_SMR ( 0) // Source Mode Register#define AIC_SVR (128) // Source Vector Register#define AIC_IVR (256) // IRQ Vector Register#define AIC_FVR (260) // FIQ Vector Register#define AIC_ISR (264) // Interrupt Status Register#define AIC_IPR (268) // Interrupt Pending Register#define AIC_IMR (272) // Interrupt Mask Register#define AIC_CISR (276) // Core Interrupt Status Register#define AIC_IECR (288) // Interrupt Enable Command Register#define AIC_IDCR (292) // Interrupt Disable Command Register⌨️ 快捷键说明
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