📄 at91sam9263_inc.h
字号:
// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- // *****************************************************************************// SOFTWARE API DEFINITION FOR External Bus Interface 1// *****************************************************************************// *** Register offset in AT91S_EBI1 structure ***#define EBI1_DUMMY ( 0) // Dummy register - Do not use// *****************************************************************************// SOFTWARE API DEFINITION FOR AHB Matrix Interface// *****************************************************************************// *** Register offset in AT91S_MATRIX structure ***#define MATRIX_MCFG0 ( 0) // Master Configuration Register 0 #define MATRIX_MCFG1 ( 4) // Master Configuration Register 1 #define MATRIX_MCFG2 ( 8) // Master Configuration Register 2 #define MATRIX_MCFG3 (12) // Master Configuration Register 3 #define MATRIX_MCFG4 (16) // Master Configuration Register 4 #define MATRIX_MCFG5 (20) // Master Configuration Register 5 #define MATRIX_MCFG6 (24) // Master Configuration Register 6 #define MATRIX_MCFG7 (28) // Master Configuration Register 7 #define MATRIX_MCFG8 (32) // Master Configuration Register 8 #define MATRIX_SCFG0 (64) // Slave Configuration Register 0#define MATRIX_SCFG1 (68) // Slave Configuration Register 1#define MATRIX_SCFG2 (72) // Slave Configuration Register 2#define MATRIX_SCFG3 (76) // Slave Configuration Register 3#define MATRIX_SCFG4 (80) // Slave Configuration Register 4#define MATRIX_SCFG5 (84) // Slave Configuration Register 5#define MATRIX_SCFG6 (88) // Slave Configuration Register 6#define MATRIX_SCFG7 (92) // Slave Configuration Register 7#define MATRIX_PRAS0 (128) // PRAS0#define MATRIX_PRBS0 (132) // PRBS0#define MATRIX_PRAS1 (136) // PRAS1#define MATRIX_PRBS1 (140) // PRBS1#define MATRIX_PRAS2 (144) // PRAS2#define MATRIX_PRBS2 (148) // PRBS2#define MATRIX_PRAS3 (152) // PRAS3#define MATRIX_PRBS3 (156) // PRBS3#define MATRIX_PRAS4 (160) // PRAS4#define MATRIX_PRBS4 (164) // PRBS4#define MATRIX_PRAS5 (168) // PRAS5#define MATRIX_PRBS5 (172) // PRBS5#define MATRIX_PRAS6 (176) // PRAS6#define MATRIX_PRBS6 (180) // PRBS6#define MATRIX_PRAS7 (184) // PRAS7#define MATRIX_PRBS7 (188) // PRBS7#define MATRIX_MRCR (256) // Master Remp Control Register // -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom -------- #define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type// -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm -------- // -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm -------- // -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs -------- // -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 -------- // -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 -------- // -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge -------- // -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps -------- // -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps -------- // -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- #define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x8 << 18) // (MATRIX) USB Master is Default Master#define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- #define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- #define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR2_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- #define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR3_USB (0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- #define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR4_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master// -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 -------- #define AT91C_MATRIX_FIXED_DEFMSTR5 (0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR5_USB (0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 -------- #define AT91C_MATRIX_FIXED_DEFMSTR6 (0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR6_USB (0x8 << 18) // (MATRIX) USB Master is Default Master// -------- MATRIX_SCFG7 : (MATRIX Offset: 0x5c) Slave Configuration Register 7 -------- #define AT91C_MATRIX_FIXED_DEFMSTR7 (0x3 << 18) // (MATRIX) Fixed Index of Default Master#define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR7_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master#define AT91C_MATRIX_FIXED_DEFMSTR7_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master// -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- #define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority#define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority#define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority#define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority#define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority#define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -