📄 at91sam9260_inc.h
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#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG// *****************************************************************************// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller// *****************************************************************************// *** Register offset in AT91S_AIC structure ***#define AIC_SMR ( 0) // Source Mode Register#define AIC_SVR (128) // Source Vector Register#define AIC_IVR (256) // IRQ Vector Register#define AIC_FVR (260) // FIQ Vector Register#define AIC_ISR (264) // Interrupt Status Register#define AIC_IPR (268) // Interrupt Pending Register#define AIC_IMR (272) // Interrupt Mask Register#define AIC_CISR (276) // Core Interrupt Status Register#define AIC_IECR (288) // Interrupt Enable Command Register#define AIC_IDCR (292) // Interrupt Disable Command Register#define AIC_ICCR (296) // Interrupt Clear Command Register#define AIC_ISCR (300) // Interrupt Set Command Register#define AIC_EOICR (304) // End of Interrupt Command Register#define AIC_SPU (308) // Spurious Vector Register#define AIC_DCR (312) // Debug Control Register (Protect)#define AIC_FFER (320) // Fast Forcing Enable Register#define AIC_FFDR (324) // Fast Forcing Disable Register#define AIC_FFSR (328) // Fast Forcing Status Register// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask// *****************************************************************************// SOFTWARE API DEFINITION FOR Parallel Input Output Controler// *****************************************************************************// *** Register offset in AT91S_PIO structure ***#define PIO_PER(p) ( 0 + (p) * 0x200) // PIO Enable Register#define PIO_PDR(p) ( 4 + (p) * 0x200) // PIO Disable Register#define PIO_PSR(p) ( 8 + (p) * 0x200) // PIO Status Register#define PIO_OER(p) (16 + (p) * 0x200) // Output Enable Register#define PIO_ODR(p) (20 + (p) * 0x200) // Output Disable Registerr#define PIO_OSR(p) (24 + (p) * 0x200) // Output Status Register#define PIO_IFER(p) (32 + (p) * 0x200) // Input Filter Enable Register#define PIO_IFDR(p) (36 + (p) * 0x200) // Input Filter Disable Register#define PIO_IFSR(p) (40 + (p) * 0x200) // Input Filter Status Register#define PIO_SODR(p) (48 + (p) * 0x200) // Set Output Data Register#define PIO_CODR(p) (52 + (p) * 0x200) // Clear Output Data Register#define PIO_ODSR(p) (56 + (p) * 0x200) // Output Data Status Register#define PIO_PDSR(p) (60 + (p) * 0x200) // Pin Data Status Register#define PIO_IER(p) (64 + (p) * 0x200) // Interrupt Enable Register#define PIO_IDR(p) (68 + (p) * 0x200) // Interrupt Disable Register#define PIO_IMR(p) (72 + (p) * 0x200) // Interrupt Mask Register#define PIO_ISR(p) (76 + (p) * 0x200) // Interrupt Status Register#define PIO_MDER(p) (80 + (p) * 0x200) // Multi-driver Enable Register#define PIO_MDDR(p) (84 + (p) * 0x200) // Multi-driver Disable Register#define PIO_MDSR(p) (88 + (p) * 0x200) // Multi-driver Status Register#define PIO_PPUDR(p) (96 + (p) * 0x200) // Pull-up Disable Register#define PIO_PPUER(p) (100 + (p) * 0x200) // Pull-up Enable Register#define PIO_PPUSR(p) (104 + (p) * 0x200) // Pull-up Status Register#define PIO_ASR(p) (112 + (p) * 0x200) // Select A Register#define PIO_BSR(p) (116 + (p) * 0x200) // Select B Register#define PIO_ABSR(p) (120 + (p) * 0x200) // AB Select Status Register#define PIO_OWER(p) (160 + (p) * 0x200) // Output Write Enable Register#define PIO_OWDR(p) (164 + (p) * 0x200) // Output Write Disable Register#define PIO_OWSR(p) (168 + (p) * 0x200) // Output Write Status Register// *****************************************************************************// SOFTWARE API DEFINITION FOR Clock Generator Controler// *****************************************************************************// *** Register offset in AT91S_CKGR structure ***#define CKGR_MOR ( 0) // Main Oscillator Register#define CKGR_MCFR ( 4) // Main Clock Frequency Register#define CKGR_PLLAR ( 8) // PLL A Register#define CKGR_PLLBR (12) // PLL B Register// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4// *****************************************************************************// SOFTWARE API DEFINITION FOR Power Management Controler// *****************************************************************************// *** Register offset in AT91S_PMC structure ***#define PMC_SCER ( 0) // System Clock Enable Register#define PMC_SCDR ( 4) // System Clock Disable Register#define PMC_SCSR ( 8) // System Clock Status Register#define PMC_PCER (16) // Peripheral Clock Enable Register#define PMC_PCDR (20) // Peripheral Clock Disable Register#define PMC_PCSR (24) // Peripheral Clock Status Register#define PMC_MOR (32) // Main Oscillator Register#define PMC_MCFR (36) // Main Clock Frequency Register#define PMC_PLLAR (40) // PLL A Register#define PMC_PLLBR (44) // PLL B Register#define PMC_MCKR (48) // Master Clock Register#define PMC_PCKR (64) // Programmable Clock Register#define PMC_IER (96) // Interrupt Enable Register#define PMC_IDR (100) // Interrupt Disable Register#define PMC_SR (104) // Status Register#define PMC_IMR (108) // Interrupt Mask Register⌨️ 快捷键说明
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