chip_sja1000p.h

it s free for can driver prelican mode

#ifndef __CHIP_SJA1000P_H__
#define __CHIP_SJA1000P_H__

/* SJA1000 CAN driver (PeliCAN mode) - Paul Miller <[e-mail]> */

#include "io.h"
#include "c6xdsk_aux.h"

#define SJA1000_CLK_HZ				24000000
#define SJA1000_CLK_KHZ				(SJA1000_CLK_HZ/1000)
#define SJA1000_IRQ					4
#define SJA1000_BASE				(AUX_ADDR|AUX_CAN_CS)
#define SJA1000_ADDR				(SJA1000_BASE + 0x0000)
#define SJA1000_DATA				(SJA1000_BASE + 0x0004)
#define SJA1000_IRQ_ENABLE()		(IER |= (1<<SJA1000_IRQ))
#define SJA1000_IRQ_DISABLE()		(IER &= ~(1<<SJA1000_IRQ))

#define CAN_QLENGTH					10
#define CAN_MSGLEN					8

#define CAN_FLAGS_EXT				0x01
#define CAN_FLAGS_RTR				0x02

typedef struct {
	QUE_Elem elem;
	unsigned int timehstamp;
	unsigned int timelstamp;
	unsigned int id;
	unsigned int flags;
	unsigned int len;
	unsigned int data[CAN_MSGLEN];
} CAN_Obj_t;

extern far SEM_Obj SEM_CANrx;
extern far QUE_Obj QUE_CANrx_free;
extern far QUE_Obj QUE_CANrx_msg;

extern far SEM_Obj SEM_CANtx;
extern far QUE_Obj QUE_CANtx_free;
extern far QUE_Obj QUE_CANtx_msg;



#ifdef __CHIP_SJA1000P_REG

/* mode register */
#define SJA1000_MOD_RM		BIT0	// reset mode
#define SJA1000_MOD_LOM		BIT1	// listen only mode
#define SJA1000_MOD_SFM		BIT2	// self test mode
#define SJA1000_MOD_AFM		BIT3	// acceptance filter mode
#define SJA1000_MOD_SM		BIT4	// sleep mode

/* command register */
#define SJA1000_CMR_TR		BIT0	// transmission request
#define SJA1000_CMR_AT		BIT1	// abort transmission
#define SJA1000_CMR_RRB		BIT2	// release receive buffer
#define SJA1000_CMR_CDO		BIT3	// clear data overrun
#define SJA1000_CMR_SSR		BIT4	// self reception request

/* status register */
#define SJA1000_SR_RBS		BIT0	// receive buffer status
#define SJA1000_SR_DOS		BIT1	// data overrun status
#define SJA1000_SR_TBS		BIT2	// transmit buffer status
#define SJA1000_SR_TCS		BIT3	// transmission complete status
#define SJA1000_SR_RS		BIT4	// receive status
#define SJA1000_SR_TS		BIT5	// transmit status
#define SJA1000_SR_ES		BIT6	// error status
#define SJA1000_SR_BS		BIT7	// bus status

/* interrupt register */
#define SJA1000_IR_RI		BIT0	// receive interrupt
#define SJA1000_IR_TI		BIT1	// transmit interrupt
#define SJA1000_IR_EI		BIT2	// error interrupt
#define SJA1000_IR_DOI		BIT3	// data overrun interrupt
#define SJA1000_IR_WUI		BIT4	// wake-up interrupt
#define SJA1000_IR_EPI		BIT5	// error passive interrupt
#define SJA1000_IR_ALI		BIT6	// arbitration lost interrupt
#define SJA1000_IR_BEI		BIT7	// bus error interrupt

/* interrupt enable register */
#define SJA1000_IER_RIE		BIT0	// receive interrupt enable
#define SJA1000_IER_TIE		BIT1	// transmit interrupt enable
#define SJA1000_IER_EIE		BIT2	// error interrupt enable
#define SJA1000_IER_DOIE	BIT3	// data overrun interrupt enable
#define SJA1000_IER_WUIE	BIT4	// wake-up interrupt enable
#define SJA1000_IER_EPIE	BIT5	// error-passive interrupt enable
#define SJA1000_IER_ALIE	BIT6	// arbitration lost interrupt enable
#define SJA1000_IER_BEIE	BIT7	// bus error interrupt enable

/* bitrate register 0 */
#define SJA1000_BTR0_BRP(BRP)	((BRP) & 0x3F)		// baud rate prescaler
#define SJA1000_BTR0_SJW(SJW)	(((SJW) & 0x3) << 6)// synchro jump width

/* bitrate register 1 */
#define SJA1000_BTR1_TSEG1(S)	((S) & 0x0F)		// time segment 1
#define SJA1000_BTR1_TSEG2(S)	(((S) & 0x7) << 4)	// time segment 2
#define SJA1000_BTR1_SAM		BIT7				// sampling

/* output control register */
#define SJA1000_OCR_OCMODE0	BIT0	// output control mode 0
#define SJA1000_OCR_OCMODE1	BIT1	// output control mode 1
#define SJA1000_OCR_OCPOL0	BIT2	// output control polarity 0
#define SJA1000_OCR_OCTN0	BIT3	// output control transistor N0
#define SJA1000_OCR_OCTP0	BIT4	// output control transistor P0
#define SJA1000_OCR_OCPOL1	BIT5	// output control polarity 1
#define SJA1000_OCR_OCTN1	BIT6	// output control transistor N1
#define SJA1000_OCR_OCTP1	BIT7	// output control transistor P1

/* clock divide register */
#define SJA1000_CDR_CLKOUT	BIT3	// clock off
#define SJA1000_CDR_RXINTEN	BIT5	// rx interrupt enable
#define SJA1000_CDR_CBP		BIT6	// input comparator bypass
#define SJA1000_CDR_CANMODE	BIT7	// can mode (0=BasicCAN 1=PeliCAN)

/* arbitration lost register */
#define SJA1000_ALC_CODE(CODE)	((CODE) & 0x1F)

/* error code capture register */
#define SJA1000_ECC_SEG(SEG)	((SEG) & 0x1F)
#define SJA1000_ECC_DIR			BIT5
#define SJA1000_ECC_ERRC(ERRC)	(((ERRC) & (0x03)) << 6)

/* register addresses */
#define SJA1000_MOD			0	// control register
#define SJA1000_CMR			1	// command register
#define SJA1000_SR			2	// status register
#define SJA1000_IR			3	// interrupt register
#define SJA1000_IER			4	// interrupt enable register
#define SJA1000_BTR0		6	// bus timing 0 register
#define SJA1000_BTR1		7	// bus timing 1 register
#define SJA1000_OCR			8	// output control register
#define SJA1000_ALC			11	// arbitration lost capture
#define SJA1000_ECC			12	// error code  capture
#define SJA1000_EWLR		13	// error warning limit register
#define SJA1000_RXERR		14	// RX error counter
#define SJA1000_TXERR		15	// TX error counter
#define SJA1000_FRAME		16	// frame information
#define SJA1000_MSGID		17	// message id byte 0
#define SJA1000_SFFDATA		19	// message data byte 0 (standard)
#define SJA1000_EXTDATA		21	// message data byte 0 (extended)
#define SJA1000_ACR			16	// acceptance code register
#define SJA1000_AMR			20	// acceptance mask register
#define SJA1000_RMC			29	// RX message counter
#define SJA1000_CDR			31	// clock divider register

struct SJA1000_REGS {
	volatile int MOD;	// control register
	volatile int IER;	// interrupt enable register
	volatile int BTR0;	// bus timing 0 register
	volatile int BTR1;	// bus timing 1 register
	volatile int OCR;	// output control register
	volatile int EWLR;	// error warning limit register
	volatile int ACR;	// acceptance code register
	volatile int AMR;	// acceptance mask register
	volatile int CDR;	// clock divider register
};

struct SJA1000_REGS sja1000_regs;

#endif /* __CHIP_SJA1000P_REG */

/* frame register */
#define SJA1000_FRAME_DLC(DLC)	((DLC) & 0xF)	// data length code
#define SJA1000_FRAME_RTR		BIT6			// remote tx request
#define SJA1000_FRAME_EXT		BIT7			// ext frame format







int sja1000_btr(int baud, int opt_bt, int opt_sp, int sjw);
void sja1000_irq(void);
void sja1000_tx_task(void);
void sja1000_mask(int code, int mask);
void sja1000_full_reset(void);

int can_send(int id, int flags, char *buf, int length);
void can_operate_mode(void);
void can_reset_mode(void);
void init_can(int baud, int opt_bt, int opt_sp, int sjw);

#endif /* __CHIP_SJA1000P_H__ */