m5200fecend.h

mpc5200 for bsp,it is have passed built.

#define FEC_FIFO_STAT_OF			0x100000
#define FEC_FIFO_STAT_ALARM			0x020000

/* Control/Status Registers (CSR) bit definitions */

#define FEC_END_RX_START_MSK    0xfffffffc      /* quad-word alignment */
                                                /* required for rx BDs */

#define FEC_END_TX_START_MSK    0xfffffffc      /* quad-word alignment */
                                                /* required for tx BDs */
/* Ethernet CSR bit definitions */

#define FEC_END_ETH_EN          0x00000002      /* enable Ethernet operation */
#define FEC_END_ETH_DIS         0x00000000      /* disable Ethernet operation */
#define FEC_END_ETH_RES         0x00000001      /* reset the FEC */
#define FEC_END_CTRL_MASK       0x00000003      /* FEC control register mask */

/*
 * interrupt bits definitions: these are common to both the
 * mask and the event register.
 */

#define FEC_END_EVENT_HB        0x80000000      /* heartbeat error */
#define FEC_END_EVENT_BABR      0x40000000      /* babbling rx error */
#define FEC_END_EVENT_BABT      0x20000000      /* babbling tx error */
#define FEC_END_EVENT_GRA       0x10000000      /* graceful stop complete */
#define FEC_END_EVENT_TXF       0x08000000      /* tx frame */
#define FEC_END_EVENT_MII       0x00800000      /* MII transfer */
#define FEC_END_EVENT_BERR      0x00400000      /* U-bus access error */
#define FEC_END_EVENT_LCOL      0x00200000  	/* Late collision */
#define FEC_END_EVENT_COL_RL    0x00100000  	/* Collision retry limit */
#define FEC_END_EVENT_XFIFO_UN  0x00080000  	/* Transmit fifo underrun */
#define FEC_END_EVENT_FIFO_ERR  0x00040000  	/* Transmit fifo error */
#define FEC_END_EVENT_RFIFO_ERR 0x00020000  	/* Receive  fifo error */
#define FEC_END_EVENT_MSK       0xfffe0000      /* clear all interrupts */
#define FEC_END_MASK_ALL        FEC_END_EVENT_MSK    /* mask all interrupts */


/* bit masks for the interrupt level/vector CSR */

#define FEC_END_LVL_MSK         0xe0000000      /* intr level */
#define FEC_END_TYPE_MSK        0x0000000c      /* highest pending intr */
#define FEC_END_VEC_MSK         0xe000000c      /* this register mask */
#define FEC_END_RES_MSK         0x1ffffff3      /* reserved bits */
#define FEC_END_LVL_SHIFT       0x1d            /* intr level bits location */

/* transmit and receive active registers definitions */

#define FEC_END_TX_ACT          0x01000000      /* tx active bit */
#define FEC_END_RX_ACT          0x01000000      /* rx active bit */

/* MII management frame CSRs */

#define FEC_END_MII_ST          0x40000000      /* start of frame delimiter */
#define FEC_END_MII_OP_RD       0x20000000      /* perform a read operation */
#define FEC_END_MII_OP_WR       0x10000000      /* perform a write operation */
#define FEC_END_MII_ADDR_MSK    0x0f800000      /* PHY address field mask */
#define FEC_END_MII_REG_MSK     0x007c0000      /* PHY register field mask */
#define FEC_END_MII_TA          0x00020000      /* turnaround */
#define FEC_END_MII_DATA_MSK    0x0000ffff      /* PHY data field */
#define FEC_END_MII_RA_SHIFT    0x12            /* mii reg address bits */
#define FEC_END_MII_PA_SHIFT    0x17            /* mii PHY address bits */

#define FEC_END_MII_PRE_DIS     0x00000080      /* desable preamble */
#define FEC_END_MII_SPEED_25    0x00000005      /* recommended for 25Mhz CPU */
#define FEC_END_MII_SPEED_33    0x00000007      /* recommended for 33Mhz CPU */
#define FEC_END_MII_SPEED_40    0x00000008      /* recommended for 40Mhz CPU */
#define FEC_END_MII_SPEED_50    0x0000000a      /* recommended for 50Mhz CPU */
#define FEC_END_MII_SPEED_SHIFT	1		/* MII_SPEED bits location */
#define FEC_END_MII_CLOCK_MAX	2500000		/* max freq of MII clock (Hz) */
#define FEC_END_MII_MAN_DIS     0x00000000      /* disable the MII management */
                                                /* interface */
#define FEC_END_MII_SPEED_MSK   0xffffff81      /* speed field mask */

/* FIFO transmit and receive CSRs definitions */

#define FEC_END_FIFO_MSK        0x000003ff      /* FIFO rx/tx/bound mask */

/* SDMA function code CSR */

#define FEC_END_SDMA_DATA_BE    0x60000000      /* big-endian byte-ordering */
                                                /* for SDMA data transfer */

#define FEC_END_SDMA_DATA_PPC   0x20000000      /* PPC byte-ordering */
                                                /* for SDMA data transfer */

#define FEC_END_SDMA_DATA_RES   0x00000000      /* reserved value */

#define FEC_END_SDMA_BD_BE      0x18000000      /* big-endian byte-ordering */
                                                /* for SDMA BDs transfer */

#define FEC_END_SDMA_BD_PPC     0x08000000      /* PPC byte-ordering */
                                                /* for SDMA BDs transfer */


#define FEC_END_SDMA_BD_RES     0x00000000      /* reserved value */
#define FEC_END_SDMA_FUNC_0     0x00000000      /* no function code */

/* receive control/hash registers bit definitions */

#define FEC_END_RX_CTRL_PROM    0x00000008      /* promiscous mode */
#define FEC_END_RX_CTRL_MII     0x00000004      /* select MII interface */
#define FEC_END_RX_CTRL_DRT     0x00000002      /* disable rx on transmit */
#define FEC_END_RX_CTRL_LOOP    0x00000001      /* loopback mode */
#define FEC_END_RX_FR_MSK       0x000007ff      /* rx frame length mask */


/* transmit control register bit definitions */

#define FEC_END_TX_CTRL_FD      0x00000004      /* enable full duplex mode */
#define FEC_END_TX_CTRL_HBC     0x00000002      /* HB check is performed */
#define FEC_END_TX_CTRL_GRA     0x00000001      /* issue a graceful tx stop */

/* rx/tx buffer descriptors definitions */

#define FEC_END_RBD_SZ          8       /* RBD size in byte */
#define FEC_END_TBD_SZ          8       /* TBD size in byte */
#define FEC_END_TBD_MIN         6       /* min number of TBDs */
#define FEC_END_RBD_MIN         4       /* min number of RBDs */
#define FEC_END_TBD_POLL_NUM    1       /* one TBD for poll operation */
#define CL_OVERHEAD             4       /* prepended cluster overhead */
#define CL_ALIGNMENT            4       /* cluster required alignment */
#define MBLK_ALIGNMENT          4       /* mBlks required alignment */
#define FEC_END_BD_ALIGN        0x20    /* required alignment for RBDs */
#define FEC_END_MAX_PCK_SZ      (ETHERMTU + SIZEOF_ETHERHEADER          \
                                 + ETHER_CRC_LEN)

#define FEC_END_BD_STAT_OFF     0       /* offset of the status word */
#define FEC_END_BD_LEN_OFF      2       /* offset of the data length word */
#define FEC_END_BD_ADDR_OFF     4       /* offset of the data pointer word */

#define BESTCOMM_API  11

#ifndef BESTCOMM_API
/* TBD bits definitions */

#define FEC_END_TBD_RDY         0x8000          /* ready for transmission */
#define FEC_END_TBD_WRAP        0x2000          /* look at CSR5 for next bd */
#define FEC_END_TBD_INT         0x1000          /* Interrupt */
#define FEC_END_TBD_LAST        0x0800          /* last bd in this frame */
#define FEC_END_TBD_CRC         0x0400          /* transmit the CRC sequence */
#define FEC_END_TBD_DEF         0x0200          /* Append bad CRC  */
#define FEC_END_TBD_HB          0x0100          /* heartbeat error */
#define FEC_END_TBD_LC          0x0080          /* late collision */
#define FEC_END_TBD_RL          0x0040          /* retransmission limit */
#define FEC_END_TBD_UN          0x0002          /* underrun error */
#define FEC_END_TBD_CSL         0x0001          /* carrier sense lost */
#define FEC_END_TBD_RC_MASK     0x003c          /* retransmission count mask */

/* RBD bits definitions */

#define FEC_END_RBD_EMPTY       0x8000          /* ready for reception */
#define FEC_END_RBD_WRAP        0x2000          /* look at CSR4 for next bd */
#define FEC_END_RBD_INT         0x1000          /* BD interrupt bit in status */
#define FEC_END_RBD_LAST        0x0800          /* last bd in this frame */
#define FEC_END_RBD_MISS        0x0100          /* address recognition miss */
#define FEC_END_RBD_BC          0x0080          /* broadcast frame */
#define FEC_END_RBD_MC          0x0040          /* multicast frame */
#define FEC_END_RBD_LG          0x0020          /* frame length violation */
#define FEC_END_RBD_NO          0x0010          /* nonoctet aligned frame */
#define FEC_END_RBD_SH          0x0008          /* short frame error */
                                                /* not supported by the 860T */
#define FEC_END_RBD_CRC         0x0004          /* CRC error */
#define FEC_END_RBD_OV          0x0002          /* overrun error */
#define FEC_END_RBD_TR          0x0001          /* truncated frame (>2KB) */

#define FEC_END_RBD_ERR         (FEC_END_RBD_LG  |                      \
                                 FEC_END_RBD_NO  |                      \
                                 FEC_END_RBD_CRC |                      \
                                 FEC_END_RBD_OV  |                      \
                                 FEC_END_RBD_TR)
#else
#define FEC_END_RBD_EMPTY        (SDMA_BD_MASK_READY>>16)      /* ready for reception */
#define FEC_END_TBD_RDY          (SDMA_BD_MASK_READY>>16)      /* ready for transmission */
#define FEC_END_TBD_LAST         (TASK_BD_TFD>>16)             /* ready for transmission */
#define FEC_END_TBD_INT          (TASK_BD_INT>>16)             /* BD interrupt bit in status */
#define FEC_END_TBD_CRC          0

/* if RBD contains RxFIO Status at the end */
#define FEC_END_RBD_FEMPTY       0x0001          /* FIFO run empty */
#define FEC_END_RBD_ALARM        0x0002          /* FIFO alarm */
#define FEC_END_RBD_FULL         0x0004          /* FIFO is full */
#define FEC_END_RBD_FR           0x0008          /* frame data ready */
#define FEC_END_RBD_OV           0x0010          /* FIFO overflow */
#define FEC_END_RBD_UF           0x0020          /* FIFO underflow */

#define FEC_END_RBD_ERR         (FEC_END_RBD_FEMPTY  |                      \
                                 FEC_END_RBD_ALARM  |                      \
                                 FEC_END_RBD_FULL |                      \
                                 FEC_END_RBD_OV  |                      \
                                 FEC_END_RBD_UF)
#endif

#define FEC_END_CRC_POLY	0x04c11db7	/* CRC polynomium: */
						/* x^32 + x^26 + x^23 + */
						/* x^22 + x^16 + x^12 + */
						/* x^11 + x^10 + x^8  + */
						/* x^7  + x^5  + x^4  + */
						/* x^2  + x^1  + x^0  + */

#define FEC_END_HASH_MASK	0x7c000000	/* bits 27-31 */
#define FEC_END_HASH_SHIFT	0x1a		/* to get the index */

/* defines related to the PHY device */

#define FEC_END_PHY_PRE_INIT	0x0001		/* PHY info initialized */
#define FEC_END_PHY_AUTO	0x0010		/* enable auto-negotiation */
#define FEC_END_PHY_TBL		0x0020		/* use negotiation table */
#define FEC_END_PHY_100		0x0040		/* PHY may use 100Mbit speed */
#define FEC_END_PHY_10		0x0080		/* PHY may use 10Mbit speed */
#define FEC_END_PHY_FD		0x0100		/* PHY may use full duplex */
#define FEC_END_PHY_HD		0x0200		/* PHY may use half duplex */
#define FEC_END_PHY_MAX_WAIT	0x100		/* max delay before */
#define FEC_END_PHY_NULL	0xff		/* PHY is not present */
#define FEC_END_PHY_DEF		0x0		/* PHY's logical address */

/* allowed PHY's speeds */

#define FEC_END_100MBS		100000000       /* bits per sec */
#define FEC_END_10MBS		10000000        /* bits per sec */

/*
 * user flags: full duplex mode, loopback mode, serial interface etc.
 * the user may configure some of this options according to his needs
 * by setting the related bits in the <userFlags> field of the load string.
 */

#define FEC_END_USR_PHY_NO_AN	0x00000001	/* do not auto-negotiate */
#define FEC_END_USR_PHY_TBL	0x00000002	/* use negotiation table */
#define FEC_END_USR_PHY_NO_FD	0x00000004	/* do not use full duplex */
#define FEC_END_USR_PHY_NO_100	0x00000008	/* do not use 100Mbit speed */
#define FEC_END_USR_PHY_NO_HD	0x00000010	/* do not use half duplex */
#define FEC_END_USR_PHY_NO_10	0x00000020	/* do not use 10Mbit speed */
#define FEC_END_USR_PHY_ISO	0x00000100	/* isolate a PHY */
#define FEC_END_USR_SER		0x00000200	/* 7-wire serial interface */
#define FEC_END_USR_LOOP	0x00000400	/* loopback mode */
						/* only use it for testing */
#define FEC_END_USR_HBC		0x00000080	/* perform heartbeat control */

#define FEC_END_TBD_OK		0x1		/* the TBD is a good one */
#define FEC_END_TBD_BUSY	0x2		/* the TBD has not been used */
#define FEC_END_TBD_ERROR	0x4		/* the TBD is errored */

#define PKT_TYPE_MULTI		0x1	/* packet with a multicast address */
#define PKT_TYPE_UNI		0x2	/* packet with a unicast address */
#define PKT_TYPE_NONE		0x4	/* address type is not meaningful */

#define BUF_TYPE_CL		0x1	/* this's a cluster pointer */
#define BUF_TYPE_MBLK		0x2	/* this's a mblk pointer */
#define BUF_TYPE_LOCAL		0x4	/* local TX buffer (not from netBufLib) */

/* frame descriptors definitions */

typedef char *				FEC_END_BD_ID;
typedef FEC_END_BD_ID	  	FEC_END_TBD_ID;
typedef FEC_END_BD_ID	  	FEC_END_RBD_ID;

/* MII definitions */

#define ETHER_CRC_LEN		0x4	/* CRC length in bytes */
#define MII_MAX_PHY_NUM		0x20	/* max number of attached PHYs */

#define MII_CTRL_REG		0x0	/* Control Register */