m5200.h

mpc5200 for bsp,it is have passed built.

#define I2C_CR(num)			((volatile UINT32 *) (I2C_BASE(num) + I2C_CR_OFF))
#define I2C_SR(num)			((volatile UINT32 *) (I2C_BASE(num) + I2C_SR_OFF))
#define I2C_DIO(num)		((volatile UINT32 *) (I2C_BASE(num) + I2C_DIO_OFF))

#define I2C_ICR				((volatile UINT32 *) (I2C_BASE_ADRS + I2C_ICR_OFF))



/*----------------------------------------------------------- */
/* GPIO_STD 										   0x0B00 */
/*----------------------------------------------------------- */

/* MBAR to GPIO_STD */
#define MBAR_GPIO_STD      0x0B00

#define GPIO_STD_BASE_ADRS	(MBAR_VALUE + MBAR_GPIO_STD)

/* Offset GPIO_STD to register */

#define GPIO_STD_PORT_CONFIG	0x00  /* long */
	
#define GPIO_PCR_OFF			0x00  /* GPIO Port Configuration Register */
#define GPIO_SEN_OFF			0x04  /* GPIO Enable Register */
#define GPIO_SOD_OFF			0x08  /* GPIO Open Drain Type Register */
#define GPIO_SDD_OFF			0x0c  /* GPIO Data Direction Register */
#define GPIO_SDO_OFF			0x10  /* GPIO Data Output Register */
#define GPIO_SDI_OFF			0x14  /* GPIO Data Input Register */
#define GPIO_OOE_OFF			0x18  /* GPIO Output Only Enable Register */
#define GPIO_ODO_OFF			0x1c  /* GPIO Output Data Register Out Register */
#define GPIO_SIE_OFF			0x20  /* GPIO Simple Interrupt Enable Register */
#define GPIO_SIOD_OFF			0x24  /* GPIO Simple Interrupt Open Drain Emulation Register */
#define GPIO_SIDD_OFF			0x28  /* GPIO Simple Interrupt Data Direction Register */
#define GPIO_SIDO_OFF			0x2c  /* GPIO Simple Interrupt Data Out Register */
#define GPIO_SIIE_OFF			0x30  /* GPIO Simple Interrupt Enable Register */
#define GPIO_SIIT_OFF			0x34  /* GPIO Simple Interrupt Type Register */
#define GPIO_SIME_OFF			0x38  /* GPIO Simple Interrupt Master Enable Register */
#define GPIO_SIST_OFF			0x3c  /* GPIO Simple Interrupt Status Register */
			
	

#define GPIO_PCR				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_PCR_OFF))
#define GPIO_SEN				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SEN_OFF))
#define GPIO_SOD				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SOD_OFF))
#define GPIO_SDD				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SDD_OFF))
#define GPIO_SDO				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SDO_OFF))
#define GPIO_SDI				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SDI_OFF))
#define GPIO_OOE				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_OOE_OFF))
#define GPIO_ODO				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_ODO_OFF))
#define GPIO_SIE				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIE_OFF))
#define GPIO_SIOD				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIOD_OFF))
#define GPIO_SIDD				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIDD_OFF))
#define GPIO_SIDO				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIDO_OFF))
#define GPIO_SIIE				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIIE_OFF))
#define GPIO_SIIT				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIIT_OFF))
#define GPIO_SIME				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIME_OFF))
#define GPIO_SIST				((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_SIST_OFF))
	
			

#define GPIO_STD_PC_ETH_MASK     0x000F0000
#define GPIO_STD_PC_ETH_18WIRE   0x00050000

#define GPIO_STD_PC_PCI_MASK     0x00008000
#define GPIO_STD_PC_PCI_ENABLED  0x00000000
#define GPIO_STD_PC_PCI_DISABLED 0x00000800

#define GPIO_STD_PORTCFG		((volatile UINT32 *) (GPIO_STD_BASE_ADRS + GPIO_STD_PORT_CONFIG))

#define GPIO_STD_PC_USB_MASK     0x00007000
#define GPIO_STD_PC_USB_1_ONLY   0x00001000
#define GPIO_STD_PC_USB_2_ETH    0x00011000
#define GPIO_STD_PC_USB_2_PSC3   0x00010100

#define GPIO_STD_PC_USB_SE_MODE  0x00004000
#define GPIO_STD_PC_USB_DM_MODE  0x00000000

/* i=0: PSC1; i=1: PSC2, i=3: PSC2, i=7: PSC6 */
#define PSC1_PORT	0
#define PSC2_PORT	1
#define PSC3_PORT	2
#define PSC6_PORT	7

#define GPIO_STD_PC_PSC_SHIFT(i,v) ((v)<<(4*i))
#define GPIO_STD_PC_PSC_MASK(i)    GPIO_STD_PC_PSC_SHIFT(i,0xF)
#define GPIO_STD_PC_PSC_UART(i)    GPIO_STD_PC_PSC_SHIFT(i,0x4)
#define GPIO_STD_PC_PSC_UART_CD(i) GPIO_STD_PC_PSC_SHIFT(i,0x5)

#define GPIO_STD_PC_PSC6_MASK    0x00700000	/* bits 9-11 */
#define GPIO_STD_PC_PSC6_UART    0x00500000	/* 101b = IrDa/UART */

/*----------------------------------------------------------- */
/* GPIO_WKUP										   0x0C00 */
/*----------------------------------------------------------- */

/* MBAR to GPIO_WKUP */
#define MBAR_GPIO_WKUP     0x0C00

#define GPIO_WKUP_BASE_ADRS	(MBAR_VALUE + MBAR_GPIO_WKUP)

/* Offset GPIO_WKUP to register */

#define GPIO_WKUP_WE  0x00  /* long, write enable */
#define GPIO_WKUP_OD  0x04  /* long, open drain */
#define GPIO_WKUP_DD  0x08  /* long, data direction */
#define GPIO_WKUP_DO  0x0C  /* long, data value out */
#define GPIO_WKUP_IE  0x10  /* long, interrupt enable */
#define GPIO_WKUP_SIE 0x14  /* long, simple interrupt enable */
#define GPIO_WKUP_IT  0x18  /* long, interrupt type */
#define GPIO_WKUP_ME  0x1C  /* long, data value outmaster enable */
#define GPIO_WKUP_DI  0x20  /* long, data input */
#define GPIO_WKUP_SR  0x24  /* long, sataus register */


#define GPW_WE			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_WE))
#define GPW_OD			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_OD))
#define GPW_DD			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_DD))
#define GPW_DO			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_DO))
#define GPW_IE			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_IE))
#define GPW_SIE			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_SIE))
#define GPW_IT			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_IT))
#define GPW_ME			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_ME))
#define GPW_DI			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_DI))
#define GPW_SR			((volatile UINT32 *) (GPIO_WKUP_BASE_ADRS + GPIO_WKUP_SR))


/*----------------------------------------------------------- */
/* PCI												   0x0D00 */
/*----------------------------------------------------------- */

#define MBAR_PCI		0xD00

#define PCI_BASE_ADRS	(MBAR_VALUE + MBAR_PCI)

/* Type 0 Configuration Header */
#define PCI_SCR_OFF		0x04 /* Status/Command register */
#define PCI_CR1_OFF		0x0c /* Configuration  1 register */
#define PCI_BAR0_OFF	0x10 /* Base address register 0 */
#define PCI_BAR1_OFF	0x14 /* Base address register 1 */

/* General Control/Status */
#define PCI_GSCR_OFF	0x60 /* Global Status/Control Register */
#define PCI_TBATR0_OFF	0x64 /* Target Base Address Translation Register 0 */
#define PCI_TBATR1_OFF	0x68 /* Target Base Address Translation Register 1 */
#define PCI_TCBR_OFF	0x6C /* Target Control Register */
#define PCI_IW0BTAR_OFF	0x70 /* Initiator Window 0 Base/Translation Addr Reg */
#define PCI_IW1BTAR_OFF	0x74 /* Initiator Window 1 Base/Translation Addr Reg */
#define PCI_IW2BTAR_OFF	0x78 /* Initiator Window 2 Base/Translation Addr Reg */
#define PCI_IWCR_OFF	0x80 /* Initiator Window Configuration Register */
#define PCI_ICR_OFF		0x84 /* Initiator Control Register */
#define PCI_ISR_OFF		0x88 /* Initiator Status Register */
#define PCI_ARB_OFF		0x8C /* PCI Arbiter Register */
#define PCI_CAR_OFF		0xF8 /* Configuration Address Register */

#define PCISCR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_SCR_OFF))
#define PCICR1		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_CR1_OFF))
#define PCIBAR0		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_BAR0_OFF))
#define PCIBAR1		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_BAR1_OFF))
#define PCIGSCR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_GSCR_OFF))
#define PCITBATR0	((volatile UINT32 *)(PCI_BASE_ADRS + PCI_TBATR0_OFF))
#define PCITBATR1	((volatile UINT32 *)(PCI_BASE_ADRS + PCI_TBATR1_OFF))
#define PCITCBR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_TCBR_OFF))
#define PCIIW0BTAR	((volatile UINT32 *)(PCI_BASE_ADRS + PCI_IW0BTAR_OFF))
#define PCIIW1BTAR	((volatile UINT32 *)(PCI_BASE_ADRS + PCI_IW1BTAR_OFF))
#define PCIIW2BTAR	((volatile UINT32 *)(PCI_BASE_ADRS + PCI_IW2BTAR_OFF))
#define PCIIWCR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_IWCR_OFF))
#define PCIICR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_ICR_OFF))
#define PCIISR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_ISR_OFF))
#define PCIARB		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_ARB_OFF))
#define PCICAR		((volatile UINT32 *)(PCI_BASE_ADRS + PCI_CAR_OFF))

/* Command/Status register */
#define PCISCR_B				0x00000004	/* bus master enable */

/* Cconfiguration 1 register */
#define PCICR1_LAT_MASK		    0x0000ff00
#define PCICR1_LAT_SHIFT		8

/* Global Status/Control Register */
#define PCIGSCR_BM				0x40000000
#define PCIGSCR_PE				0x20000000
#define PCIGSCR_SE				0x10000000
#define PCIGSCR_BME				0x00004000
#define PCIGSCR_PEE				0x00002000
#define PCIGSCR_SEE				0x00001000

/* IW Conf reg */

#define PCIIWCR_ENABLE			0x1
#define PCIIWCR_MEM				0x0
#define PCIIWCR_IO				0x8

#define PCIIWCR_READ_LINE		0x2
#define PCIIWCR_READ_MULTI		0x4
#define PCIIWCR_READ_SINGLE		0x0

/* Initiator Control Register */
#define PCIICR_REE				0x04000000
#define PCIICR_IAE				0x02000000
#define PCIICR_TAE				0x01000000

/* Initiator Status Register */
#define PCIISR_RE				0x04000000
#define PCIISR_IA				0x02000000
#define PCIISR_TA				0x01000000

/* PCI Arbiter Register */
#define PCIARB_RESET			0x01000000

/*-----------------------------------------------------------*/
/* USB 											      0x1000 */
/*-----------------------------------------------------------*/

#define MBAR_USB			0x1000

#define USB_BASE_ADRS		(MBAR_VALUE + MBAR_USB)

/*-----------------------------------------------------------*/
/* SMDA 											  0x1200 */
/*-----------------------------------------------------------*/

#define MBAR_SDMA			0x1200

#define SDMA_BASE_ADRS		(MBAR_VALUE + MBAR_SDMA)

#define SDMA_PTD_CTRL_OFF	0x10

#define SDMA_PTD_CTRL_PE	0x00000001

#define SDMA_PTD_CTRL		((volatile UINT32 *) (SDMA_BASE_ADRS + SDMA_PTD_CTRL_OFF))

/*-----------------------------------------------------------*/
/* XLB												  0x1F00 */
/*-----------------------------------------------------------*/

#define MBAR_XLB		0x1F00

#define XLB_CR_OFF		0x40 /* arbiter configuration register */
#define XLB_VR_OFF		0x44 /* arbiter version register */
#define XLB_SR_OFF		0x48 /* arbiter status register */
#define XLB_IER_OFF		0x4C /* arbiter interrupt enable register */
#define XLB_ACR_OFF		0x50 /* arbiter address capture register */
#define XLB_BSCR_OFF	0x54 /* arbiter bus signal capture register */
#define XLB_ATTOR_OFF	0x58 /* arbiter addr tenure timeout register */
#define XLB_DTTOR_OFF	0x5C /* arbiter data tenure timeout register */
#define XLB_BATOR_OFF	0x60 /* arbiter bus activity timeout register */
#define XLB_MPER_OFF	0x64 /* arbiter master prio enable register */
#define XLB_MPR_OFF		0x68 /* arbiter master prio register */
#define XLB_BAR_OFF		0x6C /* arbiter base address register */
#define XLB_SWR_OFF		0x70 /* arbiter snoop window register */

#define XLB_BASE_ADRS	(MBAR_VALUE + MBAR_XLB)

#define XLB_CR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_CR_OFF))
#define XLB_SR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_SR_OFF))
#define XLB_IER	   		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_IER_OFF))
#define XLB_ACR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_ACR_OFF))
#define XLB_BSCR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BSCR_OFF))
#define XLB_ATTOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_ATTOR_OFF))
#define XLB_DTTOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_DTTOR_OFF))
#define XLB_BATOR		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BATOR_OFF))
#define XLB_MPER		((volatile UINT32 *)(XLB_BASE_ADRS + XLB_MPER_OFF))
#define XLB_MPR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_MPR_OFF))
#define XLB_BAR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_BAR_OFF))
#define XLB_SWR			((volatile UINT32 *)(XLB_BASE_ADRS + XLB_SWR_OFF))

 
/* arbiter configuration register */

#define XLB_CR_PLDIS_MASK		0x80000000	/* pipeline disabled */
#define XLB_CR_PLDIS_DISABLED	0x80000000
#define XLB_CR_PLDIS_ENABLED	0x00000000
#define XLB_CR_SE_MASK			0x00008000	/* snoop enabled */
#define XLB_CR_SE_DISABLED		0x00000000
#define XLB_CR_SE_ENABLED		0x00008000
#define XLB_CR_USE_WWF_MASK		0x00004000	/* force write-write-flush */
#define XLB_CR_USE_WWF_DISABLED	0x00000000
#define XLB_CR_USE_WWF_ENABLED	0x00004000
#define XLB_CR_TBEN_MASK		0x00002000	/* timebase enable */
#define XLB_CR_TBEN_DISABLED	0x00000000
#define XLB_CR_TBEN_ENABLED		0x00002000
#define XLB_CR_WS_MASK			0x00000800	/* minimum wait state */
#define XLB_CR_WS_0				0x00000000
#define XLB_CR_WS_1				0x00000800
#define XLB_CR_PM_MASK			0x00000060	/* parking mode */
#define XLB_CR_PM_NON			0x00000000
#define XLB_CR_PM_MOST_RECENT	0x00000040
#define XLB_CR_PM_SELECTED		0x00000060
#define XLB_CR_SP_MASK			0x00000700	/* selected parked master */
#define XLB_CR_SP_SHIFT			8
#define XLB_CR_BA_MASK			0x00000008	/* bus activity TO enable */
#define XLB_CR_BA_DISABLED		0x00000000
#define XLB_CR_BA_ENABLED		0x00000008
#define XLB_CR_DT_MASK			0x00000008	/* data tenure TO enable */
#define XLB_CR_DT_DISABLED		0x00000000
#define XLB_CR_DT_ENABLED		0x00000008
#define XLB_CR_AT_MASK			0x00000008	/* address tenure TO enable */
#define XLB_CR_AT_DISABLED		0x00000000
#define XLB_CR_AT_ENABLED		0x00000008

/* arbiter status register */
#define XLB_SR_SEA_MASK			0x00000100	/* slave error ack */
#define XLB_SR_MM_MASK			0x00000080	/* multiple masters */
#define XLB_SR_TTA_MASK			0x00000040	/* TT address only */
#define XLB_SR_TTR_MASK			0x00000020	/* TT reserved */
#define XLB_SR_ECW_MASK			0x00000010	/* external control word R/W */
#define XLB_SR_TTM_MASK			0x00000008	/* TBST/TSIZ mismatch */
#define XLB_SR_BA_MASK			0x00000004	/* bus activity timeout */
#define XLB_SR_DT_MASK			0x00000002	/* data tenure timeout */
#define XLB_SR_AT_MASK			0x00000001	/* address tenure timeout */
#define XLB_SR_CLEAR_ALL		(XLB_SR_ECW_MASK|XLB_SR_DT_MASK|XLB_SR_AT_MASK)

/* arbiter interrupt enable register */
#define XLB_IER_SEAE_MASK		0x00000100	/* slave error ack */
#define XLB_IER_MME_MASK		0x00000080	/* multiple masters */
#define XLB_IER_TTAE_MASK		0x00000040	/* TT address only */
#define XLB_IER_TTRE_MASK		0x00000020	/* TT reserved */
#define XLB_IER_ECWE_MASK		0x00000010	/* external control word R/W */
#define XLB_IER_TTME_MASK		0x00000008	/* TBST/TSIZ mismatch */
#define XLB_IER_BAE_MASK		0x00000004	/* bus activity timeout */
#define XLB_IER_DTE_MASK		0x00000002	/* data tenure timeout */
#define XLB_IER_ATE_MASK		0x00000001	/* address tenure timeout */

/* arbiter bus signal capture register */