m5200intr.c

mpc5200 for bsp,it is have passed built.

    intMask = *ICTL_CPMIMR;

#if 0
TBD
    /* lock all levels inferior to the interrupt detected */

    /* those with lower priority level are all in mskPIMR[isr_PSe] */
    *ICTL_PIMR |= mskPIMR[isr_PSe];
    /* those with same priority level are all in lvlPIMR[isr_PSe]
       mask only those bits on the right hand side and including isr_PSe */
    *ICTL_PIMR |= (lvlPIMR[isr_PSe] & ( ( 1 << (32-isr_PSe) ) - 1));
#else
    *ICTL_CPMIMR |= ICTL_CPMIMR_MASK_ALL; /* mask all for now -> no nesting */
#endif

    /* unlock the interrupt */

#if 0
    /* TBD: remove to enable nesting */

    intUnlock (_PPC_MSR_EE);
#endif

    /* call the Interrupt Handler */

    intrVecTable[IVEC_TO_INUM(vector)].vec (intrVecTable[IVEC_TO_INUM(vector)].arg);

    /* restore the interrupt mask */

    *ICTL_CPMIMR = intMask;

    return;
    }

void m5200IntAck(int intNum)
{
    int type;

    switch (intNum) {
    case INUM_IRQ0:
	type = *ICTL_EEETR & ICTL_EEETR_ETYPE0_MASK;
	if ((type == ICTL_EEETR_ETYPE0_RISING_EDGE)
		|| (type == ICTL_EEETR_ETYPE0_FALLING_EDGE))
            *ICTL_EEETR  |= ICTL_EEETR_ECLR0_MASK; /* serviced */
	break;

    case INUM_IRQ1:
	type = *ICTL_EEETR & ICTL_EEETR_ETYPE1_MASK;
	if ((type == ICTL_EEETR_ETYPE1_RISING_EDGE)
		|| (type == ICTL_EEETR_ETYPE1_FALLING_EDGE))
            *ICTL_EEETR  |= ICTL_EEETR_ECLR1_MASK; /* serviced */
	break;

    case INUM_IRQ2:
	type = *ICTL_EEETR & ICTL_EEETR_ETYPE2_MASK;
	if ((type == ICTL_EEETR_ETYPE2_RISING_EDGE)
		|| (type == ICTL_EEETR_ETYPE2_FALLING_EDGE))
            *ICTL_EEETR  |= ICTL_EEETR_ECLR2_MASK; /* serviced */
	break;

    case INUM_IRQ3:
	type = *ICTL_EEETR & ICTL_EEETR_ETYPE3_MASK;
	if ((type == ICTL_EEETR_ETYPE3_RISING_EDGE)
		|| (type == ICTL_EEETR_ETYPE3_FALLING_EDGE))
            *ICTL_EEETR  |= ICTL_EEETR_ECLR3_MASK; /* serviced */
	break;

    default:
    }

#if 0
/* TBD: remove if 0 to enable nesting */

    if ((intNum >= INUM_CRITICAL_FIRST) && (intNum <= INUM_CRITICAL_LAST))
#if !USE_CRITICAL_INTERRUPT
        intUnlock (_PPC_MSR_EE);
#else
        intUnlock (_PPC_MSR_CE);
#endif

#endif
}

/*******************************************************************************
*
* m5200IntEnable - enable one of the Level or IRQ interrupts into the SIU
*
* RETURNS: OK, or ERROR if not applicable to intNum
*/

LOCAL int m5200IntEnable
    (
    int intNum		/* interrupt level to enable (0 - 31) */
    )
    {
    if ((intNum >= INUM_PERIPHERAL_FIRST) && (intNum <= INUM_PERIPHERAL_LAST))
    	{
	*ICTL_PIMR &= ~(1 << (31 - intNum + INUM_PERIPHERAL_FIRST));
	}
    else if (_func_sdmaIntEnableRtn && (intNum >= INUM_SDMA_FIRST) && (intNum <= INUM_SDMA_LAST))
	{
	return (_func_sdmaIntEnableRtn)(intNum);
	}
    else 
	{
	switch (intNum) {
	case INUM_IRQ0:
	    *ICTL_EEETR  |= ICTL_EEETR_EENA0_MASK;
	    break;

	case INUM_SLT1:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK0; break;

	case INUM_IRQ1:
	    *ICTL_EEETR  |= ICTL_EEETR_EENA1_MASK;
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK1; break;

	case INUM_IRQ2:
	    *ICTL_EEETR  |= ICTL_EEETR_EENA2_MASK;
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK2; break;

	case INUM_IRQ3:
	    *ICTL_EEETR  |= ICTL_EEETR_EENA3_MASK;
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK3; break;
    
	case INUM_RTC_pint:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK5; break;
    
	case INUM_RTC_sint:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK6; break;
    
	case INUM_GPIO_std:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK7; break;
    
	case INUM_GPIO_wkup:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK8; break;

	case INUM_TMR0:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK9; break;

	case INUM_TMR1:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK10; break;

	case INUM_TMR2:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK11; break;

	case INUM_TMR3:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK12; break;

	case INUM_TMR4:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK13; break;

	case INUM_TMR5:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK14; break;

	case INUM_TMR6:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK15; break;

	case INUM_TMR7:
	    *ICTL_CPMIMR &= ~ICTL_CPMIMR_MAIN_MASK16; break;

	default:
	    return ERROR;
        }
	}
    
    return OK;
    }

/*******************************************************************************
*
* m5200IntDisable - disable one of the Level or IRQ interrupts into the SIU
*
* RETURNS: OK, or ERROR if not applicable to intNum
*/

LOCAL int m5200IntDisable
    (
    int intNum		/* interrupt level to disable (0 - 31) */
    )
    {
    if ((intNum >= INUM_PERIPHERAL_FIRST) && (intNum <= INUM_PERIPHERAL_LAST))
	{
	*ICTL_PIMR |= (1 << (31 - intNum + INUM_PERIPHERAL_FIRST));
	}
    else if (_func_sdmaIntDisableRtn && (intNum >= INUM_SDMA_FIRST) && (intNum <= INUM_SDMA_LAST))
	{
	return (_func_sdmaIntDisableRtn)(intNum);
	}
    else 
    	{
	switch (intNum) {
	case INUM_IRQ0:
	    *ICTL_EEETR &= ~ICTL_EEETR_EENA0_MASK;
	    break;

	case INUM_SLT1:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK0; break;

	case INUM_IRQ1:
	    *ICTL_EEETR  &= ~ICTL_EEETR_EENA1_MASK;
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK1; break;

	case INUM_IRQ2:
	    *ICTL_EEETR  &= ~ICTL_EEETR_EENA2_MASK;
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK2; break;

	case INUM_IRQ3:
	    *ICTL_EEETR  &= ~ICTL_EEETR_EENA3_MASK;
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK3; break;
    
	case INUM_RTC_pint:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK5; break;
    
	case INUM_RTC_sint:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK6; break;
    
	case INUM_GPIO_std:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK7; break;
    
	case INUM_GPIO_wkup:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK8; break;

	case INUM_TMR0:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK9; break;

	case INUM_TMR1:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK10; break;

	case INUM_TMR2:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK11; break;

	case INUM_TMR3:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK12; break;

	case INUM_TMR4:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK13; break;

	case INUM_TMR5:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK14; break;

	case INUM_TMR6:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK15; break;

	case INUM_TMR7:
	    *ICTL_CPMIMR |= ICTL_CPMIMR_MAIN_MASK16; break;

	default:
	    return ERROR;
        }
        }
   
    return OK;
    }

int m5200IntrSetLevel(int intNum, int level)
	{
	int result;

	if ((intNum >= INUM_PERIPHERAL_FIRST) && (intNum <= INUM_PERIPHERAL_LAST))
		{
		/* valid range 0 .. 15 */
		if (level >= 0  && level <= 15)
			{
			int                 pNum      = intNum - INUM_PERIPHERAL_FIRST;
			int                 regOffset = pNum / 4;
			volatile UINT32 *   pPPR      = &ICTL_PPR[regOffset];
			int                 regShift  = (7 - pNum % 4) * 4;
			UINT32              pprBit    = 1<<pNum;
			int                 old_level;

			old_level = intLock();
			result = (*pPPR >> regShift) & 15;
			if (result  != level)
				{
				int l;

				ICTL_PPR[regOffset] &= ~(15 << regShift);
				ICTL_PPR[regOffset] |= level << regShift;
				lvlPIMR[result] &= ~pprBit;
				lvlPIMR[level] |= pprBit;
				if (result < level)	/* level increased */
					for (l=result; l < level; l++)
						mskPIMR[l] |= pprBit;
				else
					for (l=level; l < result; l++)
						mskPIMR[l] &= ~pprBit;
				}
			intUnlock(old_level);
			}
		else
			return ERROR;
		}
	else if (_func_sdmaIntSetLevelRtn && (intNum >= INUM_SDMA_FIRST) && (intNum <= INUM_SDMA_LAST))
		return(_func_sdmaIntSetLevelRtn)(intNum,level);
	else
		return ERROR; /* TBD */

	return OK;
	}

void m5200MachCheckHandler
    (
    ESFPPC *	pEsf			/* pointer to exception stack frame */
    )
    {
    EXC_INFO	excInfo;
    int		vecNum = pEsf->vecOffset;	/* exception vector number */
    REG_SET *	pRegs = &pEsf->regSet;		/* pointer to register on esf */

    extern FUNCPTR _func_excTrapRtn;

#ifdef  WV_INSTRUMENTATION
    /* windview - level 3 event logging */
    EVT_CTX_1(EVENT_EXCEPTION, vecNum);
#endif

    if ((pEsf->regSet.msr & _EXC_PROG_SRR1_TRAP) && (_func_excTrapRtn != NULL)
	&& ((*(INSTR *) pEsf->regSet.pc) == DBG_BREAK_INST))
	{
	pEsf->regSet.msr &= ~_EXC_PROG_SRR1_TRAP;
	(* _func_excTrapRtn) (pEsf, pRegs, NULL, FALSE);
	}
    else
	{
        excInfo.vecOff = vecNum;
        excInfo.cia = pEsf->regSet.pc;		/* copy cia/nia */
        excInfo.msr = pEsf->regSet.msr;		/* copy msr */
        excInfo.cr = pEsf->regSet.cr;		/* copy cr */

	excInfo.valid = (_EXC_INFO_DEFAULT | _EXC_INFO_NIA) & ~_EXC_INFO_CIA;

	if (*XLB_ACR != 0)	
	{
	    /* XLB is source */
	    excInfo.valid = excInfo.valid | _EXC_INFO_XLB;

	    excInfo.dar = *XLB_ACR;		/* use dar & dsisr for now */
	    excInfo.dsisr = *XLB_SR | *XLB_BSCR<<16; 
	    *XLB_SR = XLB_SR_CLEAR_ALL;		/* clear to free ACR/BSCR */
	}

	if ((_func_excBaseHook != NULL) &&		/* user hook around? */
	    ((* _func_excBaseHook) (vecNum, pEsf, pRegs, &excInfo)))
	    return;					/* user hook fixed it */

	if (INT_CONTEXT ())
	    {
	    if (_func_excPanicHook != NULL)		/* panic hook? */
		(*_func_excPanicHook) (vecNum, pEsf, pRegs, &excInfo);

	    reboot (BOOT_WARM_AUTOBOOT);
	    return;					/* reboot returns?! */
	    }

	/* task caused exception */

	taskIdCurrent->pExcRegSet = pRegs;		/* for taskRegs[GS]et */

	taskIdDefault ((int)taskIdCurrent);		/* update default tid */

	bcopy ((char *) &excInfo, (char *) &(taskIdCurrent->excInfo),
	       sizeof (EXC_INFO));			/* copy in exc info */

	if (_func_sigExcKill != NULL)
	    _func_sigExcKill((int) vecNum, vecNum, pRegs);

	if (_func_excInfoShow != NULL)			/* default show rtn? */
	    (*_func_excInfoShow) (&excInfo, TRUE);

	if (excExcepHook != NULL)
	    (* excExcepHook) (taskIdCurrent, vecNum, pEsf);

	taskSuspend (0);				/* whoa partner... */

	taskIdCurrent->pExcRegSet = (REG_SET *) NULL;	/* invalid after rts */
	}
    }

/*******************************************************************************
*
* m5200ExcInfoShow - print exception info
*
* NOMANUAL
*/

LOCAL void m5200ExcInfoShow 
    (
    EXC_INFO *	pExcInfo,
    BOOL	doBell
    )
    {
    FAST int vecOff = pExcInfo->vecOff;
    FAST int valid  = pExcInfo->valid;
    	
    if ((!(valid & _EXC_INFO_VEC)) || (vecOff != _EXC_OFF_MACH))
    {
        (*org_func_excInfoShow)(pExcInfo,doBell);
	return;
    }

    printExc ("\nmachine check\n", 0, 0, 0, 0, 0);	

    if (valid & _EXC_INFO_CIA)
	printExc ("Exception current instruction address: 0x%08x\n", 
		  (int) pExcInfo->cia, 0, 0, 0, 0);

    if (valid & _EXC_INFO_NIA)
	printExc ("Exception next instruction address: 0x%08x\n", 
		  (int) pExcInfo->cia, 0, 0, 0, 0);

    if (valid & _EXC_INFO_MSR)
	printExc ("Machine Status Register: 0x%08x\n", 
		  (int) pExcInfo->msr, 0, 0, 0, 0);

    if (valid & _EXC_INFO_XLB)
        printExc ("Exception access address: 0x%08x XLB status 0x%03x XLB signals 0x%03x\n", 
		  (int) pExcInfo->dar, (int) (pExcInfo->dsisr&0xffff), 
		  (int) (pExcInfo->dsisr>>16), 0, 0);

    if (valid & _EXC_INFO_XER)
        printExc ("Fixed Point Register: 0x%08x\n", 
		  (int) pExcInfo->xer, 0, 0, 0, 0);

    if (valid & _EXC_INFO_CR)
        printExc ("Condition Register: 0x%08x\n", 
		  (int) pExcInfo->cr, 0, 0, 0, 0);

#ifdef	_EXC_INFO_FPCSR
    if (valid & _EXC_INFO_FPCSR)
        printExc ("Fp Control and Status Register: 0x%08x\n", 
		  (int) pExcInfo->fpcsr, 0, 0, 0, 0);
#endif	/* _EXC_INFO_FPCSR */

    if (doBell)
	printExc ("Task: %#x \"%s\"\007\n", (int)taskIdCurrent, 
		  (int)taskName ((int)taskIdCurrent), 0, 0, 0);
    }

void m5200ExcShowInit()
{
    org_func_excInfoShow = (VOIDFUNCPTR) _func_excInfoShow;
    _func_excInfoShow = (FUNCPTR) m5200ExcInfoShow;
}