syslib.c

mpc5200 for bsp,it is have passed built.

/* sysLib.c - Motorola MPC5200 board series system-dependent library */

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "stdio.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "usrLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "drv/pci/pciAutoConfigLib.h"
#include "drv/dma/m5200Sdma.h"

/* defines */

#define ZERO    0


/* globals */

/*
 * sysSDMA is required by some of the MPC5200 drivers. It's external
 * definition can be found in m5200Sdma.h.
 */

sdma_regs *sysSDMA = (sdma_regs *)(SDMA_BASE_ADRS);


UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */
#if (FLASH_SIZE == 0x1000000)
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP),
#elif (FLASH_SIZE == 0x800000)
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_8M | _MMU_UBAT_VS | _MMU_UBAT_VP),
#elif (FLASH_SIZE == 0x400000)
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M | _MMU_UBAT_VS | _MMU_UBAT_VP),
#elif (FLASH_SIZE == 0x200000)
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_2M | _MMU_UBAT_VS | _MMU_UBAT_VP),
#elif (FLASH_SIZE == 0x100000)
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
#else
#error
#endif
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW),

    /* I BAT 1 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 2 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 3 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) |  _MMU_LBAT_CACHE_INHIBIT),

#if 1
    /* D BAT 0 - PCI prefetchable memory = 512MB */
    ((CPU_PCI_MEM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_MEM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 1 - PCI non-prefetchable memory  = 1GB */
    ((CPU_PCI_NO_PRE_MEM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1G | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_NO_PRE_MEM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 2 - PCI IO space = 256MB */
    ((CPU_PCI_IO_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_IO_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#else
    /* D BAT 0 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 1 -- disabled */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 2 - PCI IO space 0xA0000000 to 0xDF000000 */
    ((0xa0000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1G | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0xa0000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#endif

    /* D BAT 3 - MBAR space 0xxxxx0000 to 0xxxx40000 */
    ((MBAR_VALUE & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256K | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((MBAR_VALUE & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED)

};

#ifdef INCLUDE_MMU
/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory      Page Table size
 * -------------------      ---------------
 *        8 Meg              64 K
 *       16 Meg             128 K
 *       32 Meg             256 K
 *       64 Meg             512 K
 *      128 Meg               1 Meg
 *  .               .
 *  .               .
 *  .               .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
#ifdef LOCAL_MEM_ADD_LOCAL_ADRS
    {
	/* additionnal memory area */
	(void *) LOCAL_MEM_ADD_LOCAL_ADRS,
	(void *) LOCAL_MEM_ADD_LOCAL_ADRS,
	LOCAL_MEM_ADD_SIZE,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },
#endif
	
	{
	/* "Vector Table" and Interrupt Stack */
	(void *) LOCAL_MEM_LOCAL_ADRS,
	(void *) LOCAL_MEM_LOCAL_ADRS,
	(RAM_LOW_ADRS - LOCAL_MEM_LOCAL_ADRS),
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
	/* Local SDRAM  */
	(void *) RAM_LOW_ADRS,
	(void *) RAM_LOW_ADRS,
	(LOCAL_MEM_SIZE - (RAM_LOW_ADRS - LOCAL_MEM_LOCAL_ADRS)),
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
	/* 8-bit flash */
	(void *) FLASH_BASE_ADRS,
	(void *) FLASH_BASE_ADRS,
	FLASH_SIZE,
	VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_GUARDED,
	VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  | VM_STATE_GUARDED
    }
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /* INCLUDE_MMU */

int    sysCpu      = CPU;               /* system CPU type */
char * sysBootLine = BOOT_LINE_ADRS;    /* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;      /* catastrophic message area */
int    sysProcNum  = 0;				    /* processor number of this CPU */
int    sysFlags;                        /* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];    /* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];    /* name of file from which we booted */

/* locals */
LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void	sysCpuCheck (void);
char *  sysPhysMemTop (void);
void    sysDelay		(void);		/* delay 1 millisecond */
void	sysMsDelay		(UINT delay);	/* delay N millisecond(s) */

/* externals */

IMPORT UCHAR  sysInByte (ULONG);
IMPORT void   sysOutByte (ULONG, UCHAR);
IMPORT STATUS sysMemProbeSup (int length, char * src, char * dest);
IMPORT STATUS sysPciInit (void);
IMPORT STATUS sysPciInit2 (void);
IMPORT void   sysClearBATsInvalidateTLBs (void);
IMPORT STATUS sysSdmaInit (void);

/* BSP DRIVERS */
#include "intrCtl/m5200Intr.c"

#ifdef INCLUDE_GPIO
#include "sysGpioDemux.c"
#endif

#ifdef INCLUDE_AUX_CLK
#include "timer/m5200SliceTimer.c"
#endif /* INCLUDE_AUX_CLK */

#ifdef INCLUDE_MPC5200_GPT_TIMER
#include "timer/m5200GPTimer.c"
#endif /* INCLUDE_MPC5200_GPT_TIMER */

#ifdef INCLUDE_PCI
#include "sysPci.c"
#endif /* INCLUDE_PCI */

#ifdef INCLUDE_PCI_AUTOCONF
#include "sysPciAutoConfig.c"
#endif /* INCLUDE_PCI_AUTOCONF */

#include "vme/nullVme.c"
#include "sysSerial.c"
#include "timer/ppcDecTimer.c" /* PPC603 & 604 have on chip timers */
#include "sysCacheLockLib.c"

#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
#include "nvRamToFlash.c"
#include "flashMem.c"
#endif

/* network driver */
#ifdef INCLUDE_NETWORK
#include "sysNet.c"
#endif /* INCLUDE_NETWORK */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif /* INCLUDE_VWARE_LAUNCH */

#ifdef INCLUDE_WINDML
#include "sysWindML.c"
#endif /* INCLUDE_WINDML */

#ifdef INCLUDE_ATA
#include "sysAta.c"
#endif	/* INCLUDE_ATA */


/***********************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.  
*
* RETURNS: A pointer to the string.
*/

char * sysModel 
    ( 
    void
    )
    {
    UINT cpu;
    char cpuStr[80];

    /* Determine CPU type and build display string */
    cpu = CPU_TYPE;

    switch (cpu)
        {
        case CPU_TYPE_5200:
            sprintf(cpuStr, "5200B");
            break;
        default:
            sprintf (cpuStr, "xxx");
            break;
        }

    sprintf (sysModelStr, "MPC%s -- Wind River BSP.", cpuStr);

    return (sysModelStr);

    }

/***********************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.2/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev 
    (
    void
    )
    {
    return (BSP_VERSION BSP_REV);
    }
/***********************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various features of the CPU board.  It is called
* by usrInit() in usrConfig.c.  This routine sets up the control registers
* and initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user application.  It
* cannot be used to initialize interrupt vectors.
*
* RETURNS: N/A
*/

void sysHwInit 
    (
    void
    )
    {
    sysCpuCheck ();	/* Validate CPU type */

    /* set GPS port configuration */

    *GPIO_STD_PORTCFG = GPS_INIT_VALUE;

    /* set clocks */

    *CDM_CFG            = CDM_CFG_VALUE;
    *CDM_DIVIDER        = CDM_DIV_VALUE;
    *CDM_CLK_ENABLE 	= CDM_ENA_VALUE;

    /* setup XLB */

 
#ifdef SNOOP_ENABLE
   /* XLB_SWR register: WINSIZE = 256Mb, set WINBASE, DS=0 */

	*XLB_SWR = (LOCAL_MEM_LOCAL_ADRS & 0xfffff000) | 0x1B;

#endif /* SNOOP_ENABLE */

    /*
     * XLB_CR register:
     * CPU Pipeline depends on USB & PCI
     * Snooping depends on SNOOP_ENABLE, defined in config.h
     */

#ifdef SNOOP_ENABLE

#if (defined (INCLUDE_USB) || defined (INCLUDE_PCI))
    *XLB_CR = XLB_CR_PLDIS_DISABLED | XLB_CR_SE_ENABLED;
#else
    *XLB_CR = XLB_CR_PLDIS_ENABLED | XLB_CR_SE_ENABLED;
#endif

#else /* not SNOOP_ENABLE */

#if (defined (INCLUDE_USB) || defined (INCLUDE_PCI))
    *XLB_CR = XLB_CR_PLDIS_DISABLED | XLB_CR_SE_DISABLED;
#else
    *XLB_CR = XLB_CR_PLDIS_ENABLED | XLB_CR_SE_DISABLED;
#endif

#endif /* SNOOP_ENABLE */

    m5200IntrInit ();

    *XLB_CR |= XLB_CR_TBEN_ENABLED; /* start decrementer operation */

#ifdef INCLUDE_PCI
    /*  Initialize PCI driver library. */

    if ((sysPciInit()) != OK)
	{
	/* 
	 * Note, bailing to sysToMonitor() in here will probally cause 
         * an endless loop but there is little alternative at this stage.
	 * Watch the bus access lights to help detect this condition.
	 */
	sysToMonitor (BOOT_NO_AUTOBOOT);  /* BAIL */
	}
#endif