lite5200b.h

mpc5200 for bsp,it is have passed built.

#ifndef	INCLite5200h
#define	INCLite5200h

#ifdef __cplusplus
extern "C" {
#endif

#define MBAR_VALUE 0xF0000000

#include "arch/ppc/m5200.h"
#include "drv/intrCtl/m5200Intr.h"

/* Define CPU type and number of Serial channels  */

#define CPU                       PPC603 			/* CPU type                  */
#define BUS                       0      			/* bus-less board            */

#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_5200           0x8082    			/* PPC 5200 CPU */

#define N_SIO_CHANNELS            1     			/* No. serial I/O channels   */

/* Clock Parameters */

#define	SYS_CLK_RATE_MIN        10   				/* min system clock rate    */
#define	SYS_CLK_RATE_MAX        5000 				/* max system clock rate    */
#define	AUX_CLK_RATE_MIN        7    				/* min auxiliary clock rate */
#define	AUX_CLK_RATE_MAX        100000 				/* max auxiliary clock rate */

/* interrupt signal/level assignments */

#define COM1_BASE_ADR			PSC1_BASE_ADRS 		/* serial port 1 */
#define COM1_PORT_NUM			0
#define COM1_INT_LVL	        INUM_PSC1
#define COM1_INT_VEC            IV_PSC1

/* M5200 PCI Memory map */

/* Slave window that makes local (60x bus) memory visible to PCI devices */

#define CPU_PCI_SLV_MEM_LOCAL_A MBAR_VALUE

#define BUS_PCI_SLV_MEM_LOCAL_A     0x90000000	
#define BUS_PCI_SLV_MEM_LOCAL_B     0xC0000000	

/* Latency Timer value - 64 PCI clocks */

#define PCI_LAT_TIMER           0x40

/* initiator 0 - used for prefetchable memory */

#define CPU_PCI_MEM_ADRS    0x40000000  
#define PCI_MEM_SIZE        	0x10000000  
#define BUS_PCI_MEM_ADRS    0x00000000  

/* initiator 1 - used for PCI IO */
/* BUS_PCI_IO_ADRS needs to be 0 in order to support 16 bit I/O on PCI */

#define CPU_PCI_IO_ADRS     	0x70000000  
#define PCI_IO_SIZE         		0x10000000  
#define BUS_PCI_IO_ADRS     	0x70000000  


/* initiator 2 - used for non prefetchable memory */

#define CPU_PCI_NO_PRE_MEM_ADRS   0x80000000  
#define PCI_NO_PRE_MEM_SIZE        	0x10000000  
#define BUS_PCI_NO_PRE_MEM_ADRS   0xC0000000  


/* PCI IO memory adrs to CPU (60x bus) adrs */

#define PCI_IO2LOCAL(x)     ((int)(x) + CPU_PCI_IO_ADRS - BUS_PCI_IO_ADRS)

/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x)     ((int)(x) + PCI_SLV_MEM_LOCAL)

/* PCI device configuration definitions */
#ifndef PCI_CFG_FORCE
#    define PCI_CFG_FORCE	0x0     /* UNSUPPORTED */
#endif

#ifndef PCI_CFG_AUTO
#     define PCI_CFG_AUTO	0x1		/* IS SUPPORTED */
#endif
        
#ifndef PCI_CFG_NONE
#    define PCI_CFG_NONE	0x2		/* UNSUPPORTED */
#endif

#define MPC5200_PCI_BRIDGE      0

/* PCI configuration type */

#ifndef PCI_CFG_TYPE
#define PCI_CFG_TYPE		PCI_CFG_AUTO 
#endif

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)       sysPciInByte ((UINT32)x)
    IMPORT  UINT8               sysPciInByte  (UINT32 address);
#endif

#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)       sysPciInWord ((UINT32)x)
    IMPORT  UINT16              sysPciInWord  (UINT32 address);
#endif

#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)       sysPciInLong ((UINT32)x)
    IMPORT  UINT32              sysPciInLong  (UINT32 address);
#endif

#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)    sysPciOutByte ((UINT32)x,y)
    IMPORT  void                sysPciOutByte (UINT32 address, UINT8  data);
#endif

#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)    sysPciOutWord ((UINT32)x,y)
    IMPORT  void                sysPciOutWord (UINT32 address, UINT16 data);
#endif

#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)    sysPciOutLong ((UINT32)x,y)
    IMPORT  void                sysPciOutLong (UINT32 address, UINT32 data);
#endif

#define PCI_MAX_BUS		1 	 
#define PCI_MIN_DEV		0
#define PCI_MAX_DEV		30
#define PCI_MAX_FUNC		8

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20


/* CDM : Clock Distribution Module */

#define SYS_FREQ 		33000000L 			/* Ext. Clock : 33 MHz */
#define SYS_PLL_FREQ	(SYS_FREQ*16)		/* F_VCO : 528MHz */
#define XLB_CLOCK		(SYS_PLL_FREQ/4)		/* XL BUS Clock, XLB : 132MHz */
#define CORE_CLOCK_FREQ (XLB_CLOCK*3)		/* Core Clock : 396MHz */
#define IPB_CLOCK		(XLB_CLOCK/2)  		/* IP BUS Clock : 66MHz */
#define PCI_CLOCK		(IPB_CLOCK)			/* PCI BUS Clock : 66MHz */

/* CDM Configuration Register, (XLB_CLOCK,IPB_CLOCK,PCI_CLOCK) */

#define CDM_CFG_VALUE		0x00000100		/* xlb_clk=fsystem/4, ipb_clk=xlb_clk, pci_clk=ipb_clk (66M) */

/* CDM 48MHz Fractional Divider Configuration Register 
; Settings: USB:              Use internal clock
;           Irda:             Use internal clock
;           Fraction Divider: Enable
;           Div Ratio:        FVCO CLK/11 (=48MHz) for PLL div 16
*/
#define CDM_DIV_VALUE		0x00015555		

/* enable clock : 
     MEM, PCI, LocalPlus Bus, Slice Timer,
     BestComm, ATA, ETH, USB, SPI, DBLC
     PSC1
     MSCAN, I2C, Timer, GPIO 
*/
#define	CDM_ENA_VALUE		0x000FF2FF


/* Decrementer */
#define DEC_CLOCK_FREQ      XLB_CLOCK
#define	DEC_CLK_TO_INC	    4	

/* Uarts (PSC1-6) */

#define UART_CLOCK			IPB_CLOCK

#define GPS_INIT_VALUE 0x90000004

#define	TAP_DEL	0x08

#define IPBI_WSE_VALUE		0

#define LPC_CS0_BOOT_CFG_VALUE	0x00047800
#define LPC_CS_DEAD_CTRL_VALUE	0x33333331

/* the next is required in configNet.h */
#define IPB_CLOCK_LITERAL	66000000
#if (IPB_CLOCK != IPB_CLOCK_LITERAL)
#error
#endif

#define XLB_ADDR_TO		0xffff
#define XLB_DATA_TO		0xffff

/*
 * This macro returns the positive difference between two unsigned ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)	        (abs((int)a - (int)b))

#define UART_REG_ADDR_INTERVAL  1 /* addr diff of adjacent regs */


/* General */

/* Common I/O synchronizing instructions */

#undef  EIEIO
#define EIEIO                   WRS_ASM("	eieio")

#undef  EIEIO_SYNC
#define EIEIO_SYNC              WRS_ASM("	eieio;	sync")

#define IS_LITE5200B

#define FLASH_SIZE			0x01000000	/* 16 MB */

#define DRAM_BITS	     	0x1A			/* 128MB */
#define	DRAM_CHIP_SIZE		0x08000000		/* 128MB */

/*
 * Vendor DRAM configuration
 */
#define SDRAM_MODE		0x018D0000
#define SDRAM_EMODE		0x40090000

#define SDRAM_CONTROL	0x704f0f00
#define SDRAM_CONFIG1	0x73722930
#define SDRAM_CONFIG2	0x47770000
#define SDRAM_TAPDELAY	0x10000000

/* PCI */
#define MPC5200B_PCI_DEVICE_ID	0x5809
#define MPC5200B_PCI_VENDOR_ID	0x1057
#define MPC5200B_PCI_ID			((MPC5200B_PCI_DEVICE_ID << 16) | MPC5200B_PCI_VENDOR_ID)


#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif	/* INClite5200 */