rominit.s

mpc5200 for bsp,it is have passed built.

*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInitSdram)

	// R3 points to internal peripheral space.
	mfspr	r3,MBAR

	/* 2. Memory Map And Chip Select Configuration */
	
	lis	r4,HI((LOCAL_MEM_LOCAL_ADRS & 0xFFF00000) | DRAM_BITS)
	ori	r4,r4,LO((LOCAL_MEM_LOCAL_ADRS & 0xFFF00000) | DRAM_BITS)
	stw	r4,MBAR_IPBI+IPBI_SDRAM_CONF0_OFF(r3)
	eieio

	lis	r4,HI((LOCAL_MEM_LOCAL_ADRS+DRAM_CHIP_SIZE) | DRAM_BITS)
	ori	r4,r4,LO((LOCAL_MEM_LOCAL_ADRS+DRAM_CHIP_SIZE) | DRAM_BITS)
	stw	r4,MBAR_IPBI+IPBI_SDRAM_CONF1_OFF(r3)
	eieio

	/* 3. DRAM Interface Configuration */
	
	/* 3.1 Write the 'SDelay' register */

	lis	r4,HI(0x00000004)
	ori	r4,r4,LO(0x00000004)
	stw	r4,MBAR_SDRAM+0x90(r3)
	eieio
	
	/* 3.2 Configure timing */
	
	lis	r4,HI(SDRAM_CONFIG1)
	ori	r4,r4,LO(SDRAM_CONFIG1)
	stw	r4,MBAR_SDRAM+SDRAM_CONF1_OFF(r3)
	eieio

	lis	r4,HI(SDRAM_CONFIG2)
	ori	r4,r4,LO(SDRAM_CONFIG2)
	stw	r4,MBAR_SDRAM+SDRAM_CONF2_OFF(r3)
	eieio

	/* 3.3 Enable and configure the DRAM control */
    // --------chip 1----- 

	// unlock mode register 
	lis	r4,HI(SDRAM_CONTROL | 0x80000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// precharge all banks
	lis	r4,HI(SDRAM_CONTROL | 0x80000002)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000002)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	/* 4. Vendor Specific Configuration */
	
	// set mode register: extended mode 
	lis	r4,HI(SDRAM_EMODE)
	ori	r4,r4,LO(SDRAM_EMODE)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// set mode register: reset DLL 
	lis	r4,HI(SDRAM_MODE | 0x04000000)
	ori	r4,r4,LO(SDRAM_MODE | 0x04000000)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// precharge all banks
	lis	r4,HI(SDRAM_CONTROL | 0x80000002)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000002)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// auto refresh
	lis	r4,HI(SDRAM_CONTROL | 0x80000004)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000004)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// set mode register
	lis	r4,HI(SDRAM_MODE)
	ori	r4,r4,LO(SDRAM_MODE)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// normal operation
	lis	r4,HI(SDRAM_CONTROL)
	ori	r4,r4,LO(SDRAM_CONTROL)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio


    // --------chip 2----- set hi_addr of SDRAM_CTRL

	// unlock mode register 
	lis	r4,HI(SDRAM_CONTROL | 0x80000000 | 0x01000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000000 | 0x01000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// precharge all banks
	lis	r4,HI(SDRAM_CONTROL | 0x80000002 | 0x01000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000002 | 0x01000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// set mode register: extended mode 
	lis	r4,HI(SDRAM_EMODE)
	ori	r4,r4,LO(SDRAM_EMODE)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// set mode register: reset DLL 
	lis	r4,HI(SDRAM_MODE | 0x04000000)
	ori	r4,r4,LO(SDRAM_MODE | 0x04000000)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// precharge all banks
	lis	r4,HI(SDRAM_CONTROL | 0x80000002 | 0x01000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000002 | 0x01000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// auto refresh
	lis	r4,HI(SDRAM_CONTROL | 0x80000004 | 0x01000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x80000004 | 0x01000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// set mode register
	lis	r4,HI(SDRAM_MODE)
	ori	r4,r4,LO(SDRAM_MODE)
	stw	r4,MBAR_SDRAM+SDRAM_MODE_OFF(r3)
	eieio

	// normal operation
	lis	r4,HI(SDRAM_CONTROL | 0x01000000)
	ori	r4,r4,LO(SDRAM_CONTROL | 0x01000000)
	stw	r4,MBAR_SDRAM+SDRAM_CTRL_OFF(r3)
	eieio

	// return
	blr

FUNC_END(romInitSdram)

/***************************************************************************
*
* romInvalidateTLBs - invalidate the TLB's.
*
* This routine will invalidate the TLB's.
*
* SYNOPSIS
* \ss
* void romInvalidateTLBs
*     (
*     void
*     )
* \se
*
* SEE ALSO: romClearBATs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInvalidateTLBs)
	isync
	/* invalidate entries within both TLBs */
	li	r3,128
	mtctr	r3		/* CTR = 32  */
	xor	r3,r3,r3	/* r3 = 0    */
	isync			/* context sync req'd before tlbie */
tlbloop:
	tlbie	r3
	addi	r3,r3,0x1000	/* increment bits 15-19 */
	sync			/* sync instr req'd after tlbie      */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */
	blr
FUNC_END(romInvalidateTLBs)

#if 0
/***************************************************************************
*
* romMinimumBATsInit - initialize the minimum BAT's
*
* This routine will initialize the minimum BAT's register, and terun MMU on.
*
* SYNOPSIS
* \ss
* void romMinimumBATsInit
*     (
*     void
*     )
* \se
*
* NOTE: When the MMU is disabled, the processor is said to be in Real Addressing 
*       Mode. In this mode, all memory accesses are governed by a default set of 
*       bit values for the WIMG attribute bits. For data accesses, the default 
*       WIMG = 0011 and for instruction fetches default WIMG=0001. In both cases, 
*       the guarded (G) bit is set and the cache-inhibit (I) bit is clear. In 
*       other words, in real addressing mode, the entire address space of the 
*       processor is cacheable ("NOT cache-inhibited") and guarded -- independent 
*       of whether the caches are enabled or not.
*
*       The guarded attribute merely prevents out-of-order and speculative 
*       *loads*. More details are avalible in section 5.2.1.5 of the PowerPC 
*       programming environments manual for a more complete explanation of the 
*       guarded attribute. While guarded is a necessary condition for those 
*       memory spaces in which devices reside, it is not a sufficient condition. 
*       Memory accesses to devices must be both guarded and cache inhibited. 
*       Physically disabling the data cache does not provide this second, 
*       equally necessary, condition.
*
*       Above, I used the term "NOT cache-inhibited" to draw attention to an 
*       important distinction between cache-inhibited memory accesses and 
*       cacheable memory accesses that are made while the cache itself is 
*       disabled. A naive interpretation of "cacheability" holds that these two 
*       concepts are equivalent -- they are not. To prevent out-of-order 
*       *stores* to devices, we must mark the memory addresses at which those 
*       devices reside as cache inhibited. The only way to do this is to enable 
*       the MMU. So it holds that in order to enforce in-order loads AND stores, 
*       we must enable the MMU and mark the appropriate memory regions as CI & G.
*
* SEE ALSO: romClearBATs(), romInvalidateTLBs()

* RETURNS: N/A
*/

#ifdef LOCAL_MEM_ADD_LOCAL_ADRS
#define DBATL_SDRAM ((LOCAL_MEM_ADD_LOCAL_ADRS&_MMU_LBAT_BRPN_MASK)|_MMU_LBAT_CACHE_INHIBIT|_MMU_LBAT_MEM_COHERENT|_MMU_LBAT_PP_RW)
#define DBATU_SDRAM ((LOCAL_MEM_ADD_LOCAL_ADRS&_MMU_UBAT_BEPI_MASK)|_MMU_UBAT_BL_64M|_MMU_UBAT_VS|_MMU_UBAT_VP)
#else
#define DBATL_SDRAM ((LOCAL_MEM_LOCAL_ADRS&_MMU_LBAT_BRPN_MASK)|_MMU_LBAT_CACHE_INHIBIT|_MMU_LBAT_MEM_COHERENT|_MMU_LBAT_PP_RW)
#define DBATU_SDRAM ((LOCAL_MEM_LOCAL_ADRS&_MMU_UBAT_BEPI_MASK)|_MMU_UBAT_BL_64M|_MMU_UBAT_VS|_MMU_UBAT_VP)
#endif

#define DBATL_MBAR ((MBAR_VALUE&_MMU_LBAT_BRPN_MASK)|_MMU_LBAT_CACHE_INHIBIT|_MMU_LBAT_GUARDED|_MMU_LBAT_PP_RW)
#define DBATU_MBAR ((MBAR_VALUE&_MMU_UBAT_BEPI_MASK)|_MMU_UBAT_BL_256K|_MMU_UBAT_VS|_MMU_UBAT_VP)

#define DBATL_FLASH ((FLASH_BASE_ADRS&_MMU_LBAT_BRPN_MASK)|_MMU_LBAT_CACHE_INHIBIT|_MMU_LBAT_MEM_COHERENT|_MMU_LBAT_PP_RW)
#define DBATU_FLASH ((FLASH_BASE_ADRS&_MMU_UBAT_BEPI_MASK)|_MMU_UBAT_BL_16M|_MMU_UBAT_VS|_MMU_UBAT_VP)

#define DBATL_PCIIO ((CPU_PCI_IO_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED)
#define DBATU_PCIIO ((CPU_PCI_IO_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS | _MMU_UBAT_VP)

FUNC_BEGIN(romMinimumBATsInit)

	/* SDRAM */
	lis     r3, HI(DBATL_SDRAM)
	ori     r3, r3, LO(DBATL_SDRAM)
	sync
	mtspr	DBAT0L,r3		
	mtspr	IBAT0L,r3		
	isync

	lis     r3, HI(DBATU_SDRAM)	
	ori     r3, r3, LO(DBATU_SDRAM)
	sync
	mtspr	DBAT0U,r3		
	mtspr	IBAT0U,r3		
	isync

	lis     r3, HI(DBATL_MBAR)		
	ori     r3, r3, LO(DBATL_MBAR)
	sync
	mtspr	DBAT1L,r3		
	isync

	lis     r3, HI(DBATU_MBAR)
	ori     r3, r3, LO(DBATU_MBAR)	
	sync			
	mtspr	DBAT1U,r3		
	isync

	lis     r3, HI(DBATL_FLASH)		
	ori     r3, r3, LO(DBATL_FLASH)
	sync
	mtspr	DBAT2L,r3		
	isync

	lis     r3, HI(DBATU_PCIIO)
	ori     r3, r3, LO(DBATU_PCIIO)	
	sync			
	mtspr	DBAT3U,r3		
	isync

	lis     r3, HI(DBATL_PCIIO)		
	ori     r3, r3, LO(DBATL_PCIIO)
	sync
	mtspr	DBAT3L,r3		
	isync

	lis     r3, HI(DBATU_FLASH)
	ori     r3, r3, LO(DBATU_FLASH)	
	sync			
	mtspr	DBAT2U,r3		
	isync

	lis 	r3,0x0000
	mtspr	IBAT1U,r3		
	mtspr	IBAT2U,r3		
	mtspr	IBAT3U,r3		

	/* G2_LE core bat's not considered for now. Requires kernel mod */
	lis 	r3,0x0000
	mtspr	IBAT4U,r3
	mtspr	IBAT5U,r3
	mtspr	IBAT6U,r3
	mtspr	IBAT7U,r3
	mtspr	DBAT4U,r3
	mtspr	DBAT5U,r3
	mtspr	DBAT6U,r3
	mtspr	DBAT7U,r3


	mfspr	r3, HID2		/* HID2 */
	lis	r4, HI(0xFFFBFFFF)
	ori	r4, r4, LO(0xFFFBFFFF)
	and     r3, r3, r4		/* clear HBE */
	sync
	mtspr	HID2, r3		/* HID2 */
	isync

	/* Turn on Data Relocation */
	sync
	mfmsr	r3
	ori     r3, r3, _PPC_MSR_DR
	sync
	mtmsr   r3
	isync
	blr
FUNC_END(romMinimumBATsInit)
#endif

/***************************************************************************
*
* romClearBATs - clearing all the BAT's register.
*
* This routine will zero the BAT's register.
*
* SYNOPSIS
* \ss
* void romClearBATs
*     (
*     void
*     )
* \se
*
* SEE ALSO: romInvalidateTLBs(), romMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(romClearBATs)
        /* zero out the BAT registers */
	xor	r3,r3,r3
	isync
	mtspr	IBAT0U,r3	/* clear all upper BATS first */
	mtspr	IBAT1U,r3
	mtspr	IBAT2U,r3
	mtspr	IBAT3U,r3
	mtspr	IBAT4U,r3
	mtspr	IBAT5U,r3
	mtspr	IBAT6U,r3
	mtspr	IBAT7U,r3               

	mtspr	DBAT0U,r3
	mtspr	DBAT1U,r3
	mtspr	DBAT2U,r3
	mtspr	DBAT3U,r3
	mtspr	DBAT4U,r3
	mtspr	DBAT5U,r3
	mtspr	DBAT6U,r3
	mtspr	DBAT7U,r3

	mtspr	IBAT0L,r3	/* then clear lower BATS */
	mtspr	IBAT1L,r3
	mtspr	IBAT2L,r3
	mtspr	IBAT3L,r3
	mtspr	IBAT4L,r3
	mtspr	IBAT5L,r3
	mtspr	IBAT6L,r3
	mtspr	IBAT7L,r3

	mtspr	DBAT0L,r3
	mtspr	DBAT1L,r3
	mtspr	DBAT2L,r3
	mtspr	DBAT3L,r3
	mtspr	DBAT4L,r3
	mtspr	DBAT5L,r3
	mtspr	DBAT6L,r3
	mtspr	DBAT7L,r3

	isync

	/* disable BAT4-7 for now */
	mfspr	r3, HID2		/* HID2 */
	lis	r4, HI(0xFFFBFFFF)
	ori	r4, r4, LO(0xFFFBFFFF)
	and     r3, r3, r4		/* clear HBE */
	sync
	mtspr	HID2, r3		/* HID2 */
	isync

	blr
FUNC_END(romClearBATs)


/***************************************************************************
*
* LedTest
*
* RETURNS: N/A
*/
FUNC_BEGIN(LedTest)

	// R3 points to internal peripheral space.
	mfspr	r3,MBAR

	// IRDA_TX as GPIO, and Output
	lwz     r4,MBAR_GPIO_STD+GPIO_SEN_OFF(r3)
	oris	r4,r4,0x1000
	stw		r4,MBAR_GPIO_STD+GPIO_SEN_OFF(r3)
	
	lwz     r4,MBAR_GPIO_STD+GPIO_SDD_OFF(r3)
	oris	r4,r4,0x1000
	stw		r4,MBAR_GPIO_STD+GPIO_SDD_OFF(r3)

//	lwz     r4,MBAR_GPIO_STD+GPIO_SDO_OFF(r3)
	lis		r4,0x0000
	stw		r4,MBAR_GPIO_STD+GPIO_SDO_OFF(r3)

1:
	// delay
    lis 	r5, 0x1
2:
    subi    r5,r5,1
    cmpwi   r5,0
    bne     2b

	xoris	r4,r4,0x1000
	stw		r4,MBAR_GPIO_STD+GPIO_SDO_OFF(r3)

	b	1b

	blr
	
FUNC_END(LedTest)