rominit.s

mpc5200 for bsp,it is have passed built.

/* romInit.s - Wind River MPC5200 ROM initialization module */


/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

/*
change log details
------------------
01e * Removed BAT register initialisation as this prevented ROM VxWorks
      images from booting. The BAT registers are enabled when VxWorks
      itself initialises (refer to sysBatDesc in sysLib.c)
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"	
#include "arch/ppc/mmu603Lib.h"	

        /* defines */

	/* Exported internal functions */

	FUNC_EXPORT(_romInit)	/* start of system code */
	FUNC_EXPORT(romInit)	/* start of system code */
	FUNC_EXPORT(LedTest)
	FUNC_EXPORT(_LedTest)

	/* externals */

	FUNC_IMPORT(romStart)	/* system initialization routine */

        _WRS_TEXT_SEG_START

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

	bl	cold
        nop                     /* pad to 8 byte boundary */
	bl	warm

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-2001 Wind River Systems, Inc."
	.align 2

        /* usefull when used with an emulator to detect interrupts (when vector is low) */                                   
	/* .space	 0x3000 */ 

cold:
	// Setup MBAR mirror register. MBAR is at 0x80000000 after
	// reset.
	lis	r3,HI(MBAR_RESET_VALUE)
	ori	r3,r3,LO(MBAR_RESET_VALUE)
	mtspr	MBAR,r3

    /* store new MBAR value to MBAR */                             
    lis     r4,LO(MBAR_VALUE)     /* this is to load the high address part into the LSB */
    ori     r4,r4,HI(MBAR_VALUE)
    stw     r4,MBAR_IPBI(r3)
    eieio
        
        /* setup MBAR */
	lis	r3,HI(MBAR_VALUE)
	ori	r3,r3,LO(MBAR_VALUE)
	mtspr	MBAR,r3

	// Setup GPS to something meaningful

	lis	r4,HI(GPS_INIT_VALUE)
	ori	r4,r4,LO(GPS_INIT_VALUE)
	stw	r4,MBAR_GPIO_STD+GPIO_STD_PORT_CONFIG(r3)
	eieio

	// Setup CDM

	lis	r4,HI(CDM_CFG_VALUE)
	ori	r4,r4,LO(CDM_CFG_VALUE)
	stw	r4,MBAR_CDM+CDM_CFG_OFF(r3)
	eieio

	lis	r4,HI(CDM_DIV_VALUE)
	ori	r4,r4,LO(CDM_DIV_VALUE)
	stw	r4,MBAR_CDM+CDM_DIVIDER_OFF(r3)
	eieio

	lis	r4,HI(CDM_ENA_VALUE)
	ori	r4,r4,LO(CDM_ENA_VALUE)
	stw	r4,MBAR_CDM+CDM_CLK_ENABLE_OFF(r3)
	eieio
	
	
	// Initialize SDRAM controller.
	bl	romInitSdram

//	bl LedTest

	// Switch to execution from CS0
	bl	romInitCS0

	li	r24, BOOT_COLD
	bl	start			/* skip over next instruction */

			
warm:
	or	r24, r3, r3		/* startType to r24 */

start:
	/* Zero-out registers: r0 & SPRGs */

	xor     r0,r0,r0
	mtspr   272,r0
	mtspr   273,r0
	mtspr   274,r0
	mtspr   275,r0
	mtspr   276,r0
	mtspr   277,r0
	mtspr   278,r0
	mtspr   279,r0

        /* initialize the stack pointer */

        lis     sp, HI(STACK_ADRS)
        ori     sp, sp, LO(STACK_ADRS)

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn on FP
	 */

	andi.	r3, r3, 0
	ori	r3, r3, _PPC_MSR_FP
	sync
	mtmsr 	r3
	isync

	/* Init the floating point control/status register */

	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync

	/* Initialize the floating point data registers to a known state */

	bl	ifpdr_value
	.long	0x3f800000	/* 1.0 */
ifpdr_value:
	mfspr	r3,8
	lfs	f0,0(r3)
	lfs	f1,0(r3)
	lfs	f2,0(r3)
	lfs	f3,0(r3)
	lfs	f4,0(r3)
	lfs	f5,0(r3)
	lfs	f6,0(r3)
	lfs	f7,0(r3)
	lfs	f8,0(r3)
	lfs	f9,0(r3)
	lfs	f10,0(r3)
	lfs	f11,0(r3)
	lfs	f12,0(r3)
	lfs	f13,0(r3)
	lfs	f14,0(r3)
	lfs	f15,0(r3)
	lfs	f16,0(r3)
	lfs	f17,0(r3)
	lfs	f18,0(r3)
	lfs	f19,0(r3)
	lfs	f20,0(r3)
	lfs	f21,0(r3)
	lfs	f22,0(r3)
	lfs	f23,0(r3)
	lfs	f24,0(r3)
	lfs	f25,0(r3)
	lfs	f26,0(r3)
	lfs	f27,0(r3)
	lfs	f28,0(r3)
	lfs	f29,0(r3)
	lfs	f30,0(r3)
	lfs	f31,0(r3)
	sync

	/*
	 *	Set MPU/MSR to a known state
	 *	Turn off FP
	 */

	andi.	r3, r3, 0
	sync
	mtmsr 	r3
	isync

	/* Init the Segment registers */

	andi.	r3, r3, 0
	isync
	mtsr    0,r3
	isync
	mtsr    1,r3
	isync
	mtsr    2,r3
	isync
	mtsr    3,r3
	isync
	mtsr    4,r3
	isync
	mtsr    5,r3
	isync
	mtsr    6,r3
	isync
	mtsr    7,r3
	isync
	mtsr    8,r3
	isync
	mtsr    9,r3
	isync
	mtsr    10,r3
	isync
	mtsr    11,r3
	isync
	mtsr    12,r3
	isync
	mtsr    13,r3
	isync
	mtsr    14,r3
	isync
	mtsr    15,r3
	isync

	/* Turn off data and instruction cache control bits */
	
	mfspr	r3,HID0			/* r3 = HID0 */
	andi.	r3,r3,0xcfff		/* make sure lock bits are clear */
	ori	r4,r3,(_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI | _PPC_HID0_DCFI)		
                                        /* r4 has ICE,DCE,ICI,DCI bits set */
	andi.	r3,r3,0x03ff		/* r3 has enable bits cleared */
	sync
	mtspr	HID0,r4			/* HIDO = r4 */
	isync
	sync
	mtspr	HID0,r3			/* HIDO = r3 */
	isync

	bl	romClearBATs            /* clear BATs before initialise them */
#if 0
	bl	romMinimumBATsInit
#endif
	bl	romInvalidateTLBs

#if 0
	#ifdef IS_CP2
	/* pdr: strange behavior during PCI autoconfiguration if cache enabled !!! */
	/*      so leave off */
	#else
	#ifdef INCLUDE_CACHE_SUPPORT
		/* turn the Instruction cache ON for faster FLASH ROM boots */
	
	#ifdef USER_I_CACHE_ENABLE 
		ori	r3, r3, 0x8000		/* set ICE bit */
	
	        /*
	         * The setting of the instruction cache enable (ICE) bit must be
	         * preceded by an isync instruction to prevent the cache from being
	         * enabled or disabled while an instruction access is in progress.
	         */
		isync
	        mtspr   HID0, r3
	#endif
	#endif
	#endif
#endif

// bl LedTest

	/* go to C entry point */
	
        or	r3, r24, r24		/* Restore startType */
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */
        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)
        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)
        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)
	sub	r6, r6, r7
	add	r6, r6, r8 
	mtlr	r6
	blr
FUNC_END(romInit)
FUNC_END(_romInit)

/***************************************************************************
*
* romInitCS0 - MPC5200 specific initialation - set  CS0
*
* Initialize CS0 and switch to execution from there.
*
* SYNOPSIS
* \ss
* void romInitCS0
*     (
*     void
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(romInitCS0)

	// Save LR to R31.
	mflr	r31
	
	// R3 points to internal peripheral space.
	mfspr	r3,MBAR

	// Set Chip Select 0 / Boot ROM Configuration Register

	lis	r4,HI(LPC_CS0_BOOT_CFG_VALUE)
	ori	r4,r4,LO(LPC_CS0_BOOT_CFG_VALUE)
	stw	r4,MBAR_LPC+LPC_CS0_BOOT_CFG_OFF(r3)
	eieio

	// Set Chip Select Deadcycle Control Register
	// (use 1 Dead Cycle for Flash CS0)
	// (Note: leave other values untouched)

	lis	r4,HI(LPC_CS_DEAD_CTRL_VALUE)
	ori	r4,r4,LO(LPC_CS_DEAD_CTRL_VALUE)
	stw	r4,MBAR_LPC+LPC_CS_DEAD_CTRL_OFF(r3)
	eieio

	// Disable Burst for Flashes
	// (Write to Chip Select Burst Control Register)
	// (No Burst is used)

	lis	r4,0
	stw	r4,MBAR_LPC+LPC_CS_BURST_CTRL_OFF(r3)
	eieio

	// Enable CS module and external bus error signalling.
	addi	r4,0,LO(LPC_CS_CTRL_EBEE | LPC_CS_CTRL_ME)	// how unsigned?
	sth	r4,MBAR_LPC+LPC_CS_CTRL_OFF(r3)

	eieio

#define FLASH_STOP (FLASH_BASE_ADRS+FLASH_SIZE-1)

	// Set CS0 start and stop address.
	lis	r4,HI(FLASH_BASE_ADRS>>16)
	ori	r4,r4,LO(FLASH_BASE_ADRS>>16)
	stw	r4,MBAR_IPBI+IPBI_CS0_START_OFF(r3)
	eieio
	
	lis	r4,HI(FLASH_STOP>>16)
	ori	r4,r4,LO(FLASH_STOP>>16)
	stw	r4,MBAR_IPBI+IPBI_CS0_STOP_OFF(r3)
	eieio
	
	// Set optimized CS settings.
	// TODO

	// Check for boot low or boot high (IP bit in MSR).
	sync
	mfmsr	r4
	sync
	andi.	r4,r4,0x0040
	bgt	boot_high
	
boot_low:
	// CSBoot on, CS0 on
	lis	r4,HI(IPBI_WSE_VALUE | IPBI_CTRL_CSBOOT | IPBI_CTRL_CS0)
	ori	r4,r4,LO(IPBI_WSE_VALUE | IPBI_CTRL_CSBOOT | IPBI_CTRL_CS0)
	sync
	stw	r4,MBAR_IPBI+IPBI_CTRL_OFF(r3)
	isync
	eieio

	// New start address of Flash
	lis	r4,HI(FLASH_BASE_ADRS)
	ori	r4,r4,LO(FLASH_BASE_ADRS)

	// Adjust return address
	add	r31,r31,r4

	// Switch from executing in CSBoot space in CS0 space with
	// an absolute jump.
	lis	r5,HI(boot_high)
	ori	r5,r5,LO(boot_high)
    lis     r7, HI(romInit)
    ori	r7, r7, LO(romInit)
    lis     r8, HI(ROM_TEXT_ADRS)
    ori	r8, r8, LO(ROM_TEXT_ADRS)
	sub	r5, r5, r7
	add	r5, r5, r8 
	mtlr	r5
	blr

boot_high:
	// CSBoot off, CS0 on
	lis	r4,HI(IPBI_WSE_VALUE | IPBI_CTRL_CS0)
	ori	r4,r4,LO(IPBI_WSE_VALUE | IPBI_CTRL_CS0)
	sync
	stw	r4,MBAR_IPBI+IPBI_CTRL_OFF(r3)
	isync
	eieio

	// return
	mtlr	r31
	blr

FUNC_END(romInitCS0)

/***************************************************************************
*
* romInitSdram - MPC5200 specific initialation - set SDRAM controller
*
* Initialize SDRAM controller.
*
* SYNOPSIS
* \ss
* void romInitSdram
*     (