syspci.c

mpc5200 for bsp,it is have passed built.

/* sysPci.c - Motorola 5200 PCI support */

/* includes */

#include "vxWorks.h"
#include "logLib.h"
#include "taskLib.h"
#include "config.h"

#ifdef  INCLUDE_PCI

/* typedefs */

/* local */

#if defined(IS_ICECUBE) || defined (IS_ICECUBE_OLD)|| defined(IS_LITE5200B)
LOCAL void *vectorTbl[] = { IV_IRQ0 };
#elif defined(IS_CP2)
LOCAL void *vectorTbl[] = { IV_IRQ0, IV_IRQ1, IV_IRQ2, IV_IRQ3 };
#else
# error
#endif


/* include source file */

#include "drv/pci/pciConfigLib.h"
#include "pci/pciConfigLib.c" /* PCI config space access */

#include "pci/pciConfigShow.c" /* display of PCI config space */

#if 0
#ifdef INCLUDE_SHOW_ROUTINES
#include "pci/pciConfigShow.c" /* display of PCI config space */
#endif /* INCLUDE_SHOW_ROUTINES */
#endif

/* defines */

#define PCICDR		((volatile UINT32 *)(CPU_PCI_IO_ADRS))

/* forward declarations */

LOCAL STATUS sysPciSpecialCycle (int busNo, UINT32 message);
LOCAL STATUS sysPciConfigRead (int busNo, int deviceNo, int funcNo, int offset, int width, void * pData);
LOCAL STATUS sysPciConfigWrite (int busNo, int deviceNo, int funcNo, int offset, int width, ULONG data);

STATUS sysPciInit (void);

/***********************************************************************
*
* sysPciSpecialCycle - generate a special cycle with a message
*
* This routine generates a special cycle with a message.
*
* NOMANUAL
*
* RETURNS: OK
*/

LOCAL STATUS sysPciSpecialCycle
    (
    int		busNo,
    UINT32	message
    )
    {
    int deviceNo	= 0x0000001f;
    int funcNo		= 0x00000007;

    if (busNo != 0)
	return ERROR;

    *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | 0x80000000;
    PCI_OUT_LONG (PCICDR, message);
    *PCICAR = 0;

    return (OK);
    }

/***********************************************************************
*
* sysPciIntAck - generate an interrupt acknowlege  
*
* This routine generates an interrupt acknowledge 
*
* NOMANUAL
*
* RETURNS: OK
*/

int sysPciIntAck
    (
    int		busNo
    )
    {
    int deviceNo	= 0x0000001f;
    int funcNo		= 0x00000007;
    int result;

    if (busNo != 0)
	return ERROR;

    *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | 0x80000000;
    result = PCI_IN_LONG (PCICDR);
    *PCICAR = 0;

    return (result);
    }

/***********************************************************************
*
* sysPciConfigRead - read from the PCI configuration space
*
* This routine reads either a byte, word or a long word specified by
* the argument <width>, from the PCI configuration space
* This routine works around a problem in the hardware which hangs
* PCI bus if device no 12 is accessed from the PCI configuration space.
*
* RETURNS: OK, or ERROR if this library is not initialized
*
* SEE ALSO: sysPciConfigWrite()
*/

LOCAL STATUS sysPciConfigRead
    (
    int	busNo,    /* bus number */
    int	deviceNo, /* device number */
    int	funcNo,	  /* function number */
    int	offset,	  /* offset into the configuration space */
    int width,	  /* width to be read */
    void * pData /* data read from the offset */
    )
    {
    UINT8  retValByte = 0;
    UINT16 retValWord = 0;
    UINT32 retValLong = 0;
    STATUS retStat = ERROR;
    int status;
#if 0
	int key;
    int oldMask;
#endif

    switch (width)
        {
        case 1:	/* byte */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE;
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
            retValByte = PCI_IN_BYTE (PCICDR + (offset & 0x3));
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

            *((UINT8 *)pData) = retValByte;
	    retStat = ((status & PCIISR_IA) ? ERROR : OK);
            break;

        case 2: /* word */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE; 
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
	    retValWord = PCI_IN_WORD (PCICDR + (offset & 0x2));
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

            *((UINT16 *)pData) = retValWord;
	    retStat = ((status & PCIISR_IA) ? ERROR : OK);
	    break;

        case 4: /* long */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE; 
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
	    retValLong = PCI_IN_LONG (PCICDR);
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

            *((UINT32 *)pData) = retValLong;
	    retStat = ((status & PCIISR_IA) ? ERROR : OK);
            break;

        default:
            retStat = ERROR;
            break;
        }

    return retStat;
    }

/***********************************************************************
*
* sysPciConfigWrite - write to the PCI configuration space
*
* This routine writes either a byte, word or a long word specified by
* the argument <width>, to the PCI configuration space
* This routine works around a problem in the hardware which hangs
* PCI bus if device no 12 is accessed from the PCI configuration space.
*
* RETURNS: OK, or ERROR if this library is not initialized
*
* SEE ALSO: sysPciConfigRead()
*/

LOCAL STATUS sysPciConfigWrite
    (
    int	  busNo,    /* bus number */
    int	  deviceNo, /* device number */
    int	  funcNo,   /* function number */
    int	  offset,   /* offset into the configuration space */
    int   width,    /* width to write */
    ULONG data	    /* data to write */
    )
    {
    UINT32 status = OK;
#if 0
    int key;
    int oldMask;
#endif

    if ((busNo == 0) && (deviceNo == 12))
        return (ERROR);

    switch (width)
        {
        case 1:	/* byte */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE; 
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
	    PCI_OUT_BYTE ((PCICDR + (offset & 0x3)), data);
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

            break;
        case 2: /* word */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE; 
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
	    PCI_OUT_WORD ((PCICDR + (offset & 0x2)), data);
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

	    break;
        case 4: /* long */
#if 0
    	    oldMask = *PCIICR; *PCIICR  &= ~PCIICR_IAE; 
#endif
            *PCICAR = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc) | 0x80000000;
	    PCI_OUT_LONG (PCICDR, data);
            *PCICAR = 0;
    	    status = *PCIISR;
    	    *PCIISR = PCIISR_IA; /* clear */
#if 0
    	    *PCIICR = oldMask;
#endif

            break;
        default:
            return (ERROR);      
        }
    return ((status & PCIISR_IA) ? ERROR : OK);
    }

void setInitiatorWindow (int nr, UINT32 cpuBase, UINT32 busBase, UINT32 size, UINT8 mode)
{
	UINT32 cpu, bus, mask, btarValue;
	
	if ((cpuBase & 0x00ffffff) != 0)
		return;
		
	if ((busBase & 0x00ffffff) != 0)
		return;
		
	cpu = cpuBase >> 24;
	bus = busBase >> 24;
	mask = (size >> 24) - 1;

	btarValue = cpu<<24|mask<<16|bus<<8;
    
    switch (nr) {
    case 0:
    	*PCIIW0BTAR = btarValue;
		EIEIO;
    	*PCIIWCR &= 0xf0ffffff;
    	*PCIIWCR |= mode<<24;
		EIEIO;
    	break;
    case 1:
    	*PCIIW1BTAR = btarValue;
		EIEIO;
    	*PCIIWCR &= 0xfff0ffff;
    	*PCIIWCR |= mode<<16;
		EIEIO;
    	break;
    case 2:
    	*PCIIW2BTAR = btarValue;
		EIEIO;
    	*PCIIWCR &= 0xfffff0ff;
    	*PCIIWCR |= mode<<8;
		EIEIO;
    	break;
    default:
    	return;
    }
}  

/***********************************************************************
*
* sysPciInit - PCI Configuration Library Initialization
* 
* This routine initialize the PCI configuration library.
*
* RETURNS: None
*/

STATUS sysPciInit
    (
    void
    )
    {
    STATUS retVal;
    int i;

    /* set GPIO correctly -> enable PCI */
   /* *GPIO_STD_PORTCFG &= ~GPIO_STD_PC_PCI_DISABLED; */

	*GPIO_STD_PORTCFG &= ~0x8000;

    /* MPC5200 is the PCI bus master */
    *PCISCR |= PCISCR_B;

    /* Set latency timer (minimum time the bus master can keep the bus after starting a 
       transaction */
    *PCICR1 &= ~PCICR1_LAT_MASK;
    *PCICR1 |= PCI_LAT_TIMER<<PCICR1_LAT_SHIFT;

    EIEIO;

    /* m5200 as target */

#if (BUS_PCI_SLV_MEM_LOCAL_A & 0x0003FFFF)
#   error
#endif
#if (BUS_PCI_SLV_MEM_LOCAL_A & 0x3FFFFFF)
#   error
#endif
#if (CPU_PCI_SLV_MEM_LOCAL_A & 0x0003FFFF)
#   error
#endif
#if (CPU_PCI_SLV_MEM_LOCAL_B & 0x3FFFFFFF)
#   error
#endif

    *PCIBAR0   = BUS_PCI_SLV_MEM_LOCAL_A;
    *PCIBAR1   = BUS_PCI_SLV_MEM_LOCAL_B;

    *PCITBATR0 = CPU_PCI_SLV_MEM_LOCAL_A | 1; 	/* set address and enable */
    *PCITBATR1 = CPU_PCI_SLV_MEM_LOCAL_B | 1; 	/* set address and enable */

    /* m5200 as master */
    
    /* Initiator 0 for 32 bit prefetch memory */
    setInitiatorWindow (0, CPU_PCI_MEM_ADRS, BUS_PCI_MEM_ADRS, PCI_MEM_SIZE, PCIIWCR_ENABLE|PCIIWCR_MEM|PCIIWCR_READ_MULTI);

    /* Initiator 1 for IO */
    setInitiatorWindow (1, CPU_PCI_IO_ADRS, BUS_PCI_IO_ADRS, PCI_IO_SIZE, PCIIWCR_ENABLE|PCIIWCR_IO);

    /* Initiator 2 for 32 bit non-prefetch memory */
    setInitiatorWindow (2, CPU_PCI_NO_PRE_MEM_ADRS, BUS_PCI_NO_PRE_MEM_ADRS, PCI_NO_PRE_MEM_SIZE, PCIIWCR_ENABLE|PCIIWCR_MEM|PCIIWCR_READ_SINGLE);

    /* mask interrupts here, retry count 256 */
    
    *PCIICR = 0x000000FF;		/* disable CPU interrupt */
    
    /* clear any pending int */
    
    *PCIISR = PCIISR_RE|PCIISR_IA|PCIISR_TA;
    
    /* disable config space IO */

    *PCICAR = 0;

    /* clear pending errors, mask interrupts, deassert reset */

    *PCIGSCR = PCIGSCR_BM|PCIGSCR_PE|PCIGSCR_SE;

    *PCIARB = PCIARB_RESET; /* reset arbiter */
    for (i=0; i<100000;i++) ;
    *PCIARB = 0;

#if defined(IS_LITE5200B) 
	/* LITE5200B used : /IRQ0 & /IRQ1 */
    	*ICTL_EEETR &= ~((UINT32)(ICTL_EEETR_MEE|ICTL_EEETR_ETYPE0_MASK|ICTL_EEETR_ETYPE1_MASK));
    	*ICTL_EEETR |= (ICTL_EEETR_ETYPE0_LEVEL_LO|ICTL_EEETR_MEE|ICTL_EEETR_ETYPE1_LEVEL_LO);
#endif


    retVal = pciConfigLibInit (PCI_MECHANISM_0, 
		               (ULONG) sysPciConfigRead,
                               (ULONG) sysPciConfigWrite,
                               (ULONG) sysPciSpecialCycle);
    return retVal;
    }

void pciInt()
{
    UINT32 status1 = *PCIGSCR;
    UINT32 status2 = *PCIISR;
    
    *PCIGSCR |= status1; /* clear events */
    *PCIISR |= status2; /* clear events */

    if ((status1 & PCIGSCR_BM) != 0)
    {
	/* Broken master detected */

        logMsg ("PCI Error: broken master detected\n",1,2,3,4,5,6);
	
    }

    if ((status1 & PCIGSCR_PE) != 0)
    {
	/* Parity error detected */

        logMsg ("PCI Error: parity error\n",1,2,3,4,5,6);
	
    }

    if ((status1 & PCIGSCR_SE) != 0)
    {
	/* System error detected */

        logMsg ("PCI Error: system error\n",1,2,3,4,5,6);
	
    }

    if ((status2 & PCIISR_RE) != 0)
    {
	/* Retry error */

        logMsg ("PCI Error: retry count exceeded\n",1,2,3,4,5,6);
	
    }

    if ((status2 & PCIISR_IA) != 0)
    {
	/* Initiator abort */

        logMsg ("PCI Error: initiator aborted due to timeout\n",1,2,3,4,5,6);
	
    }
    
    if ((status2 & PCIISR_TA) != 0)
    {
	/* Target abort */

        logMsg ("PCI Error: target abort\n",1,2,3,4,5,6);
    }
}

STATUS sysPciInit2
    (
    void
    )
    {
    intConnect (IV_PCI_CTL, pciInt, 0);
    intEnable (INUM_PCI_CTL);
    *PCIICR  |= PCIICR_REE|PCIICR_IAE|PCIICR_TAE;
    *PCIGSCR = PCIGSCR_BME|PCIGSCR_PEE|PCIGSCR_SEE;
    return OK;
    }

void *sysPciVectorMap(int pciIntLine)
{
    /* adjust interrupts value */
    if (pciIntLine >= NELEMENTS(vectorTbl))
	{
	return (NULL);
	}

    return vectorTbl[pciIntLine];		
}

#endif /* INCLUDE_PCI */