📄 mx.h
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//--------------------------------------------------------------------------
// IP Stack
//--------------------------------------------------------------------------
// mx.h
//
// Basic gmac declarations and register definitions for Macronix 98728EC
//
// Author: Michael A. Denio
// Copyright 2000 by Texas Instruments Inc.
//--------------------------------------------------------------------------
//
// Platform Configurations
//
#ifdef DSK6711
#define HW_CE_VALUE 0x42340827
#define HW_CLOCKRATE 150
#endif
#ifdef DSK6713
#define HW_CE_VALUE 0x42340827
#define HW_CLOCKRATE 225
#endif
#ifdef TEB6416
#define HW_CE_VALUE 0xc43c502f
#define HW_CLOCKRATE 500
#endif
#ifdef DSK6416
#define HW_CE_VALUE 0xa23a4823
#define HW_CLOCKRATE 600
#endif
//
// Global Configurations
//
#define HW_CE_REG ((unsigned int*)0x1800010)
#define EXTINT_POLARITY_LOWHIGH 0 // Do not change - set below
#define EXTINT_POLARITY_HIGHLOW 1 // Do not change - set below
#define MX_EXTINT_POLARITY EXTINT_POLARITY_HIGHLOW
#define HW_IVAL 4 // Hardware interrupt index
#define HW_IFLAG (1<<(HW_IVAL))
#define MXBASE 0xA0000000 // Can be 0xA0380000 on LogicIO board
//===========================================================================
//=== START MXE.C Only ======================================================
//===========================================================================
#define HW_IEDMAVAL 8 // Value of the EDMA interrupt
#define HW_IEDMAFLAG (1<<HW_IEDMAVAL)
//----------------------------------------------------------------------------
// EXTINT5/TP1 OPERATING MODE
//
// By default, the LogicIO card uses EXTINT5 to generate framesync signals
// for EDMA operation. Some versions of the card can use TP1 as an alternate
// framesync input. The mode of operation is selected here.
//
// One of the following must be set to "0" and one must be set to "1"
#define EDMA_FS_INT 1
#define EDMA_FS_TP1 0
//----------------------------------------------------------------------------
//
// Define our external "interrupts" and required EDMA channels.
// Here, "interrupts" are really EMDA events.
// (We assume that INT4 and INT5 are hardwired to EDMA CH4 and CH5)
// (If TP1, we use EMDA CH2 for TP1, and select CH8 for TP1 chaining.)
//
#if EDMA_FS_INT
#define HW_FSIVAL 5 // EXTINT used for Frame Sync
#define EDMA_TXCHANNEL HW_IVAL
#define EDMA_RXCHANNEL HW_FSIVAL
#endif
#if EDMA_FS_TP1
// For TP1 frame sync, the TP int is our true frame sync (the signal
// from the MX chip). The EDMA transfer programmed into the TP EDMA
// resets the clock itself to retrigger an interrupt on the next
// frame sync, and then chains to "RXCHANNEL" EDMA.
#define EDMA_TXCHANNEL HW_IVAL
#define EDMA_RXCHANNEL HW_IEDMAVAL
#define EDMA_TPCHANNEL EDMA_CHA_TINT1
#endif
//===========================================================================
//=== END MXE.C Only ========================================================
//===========================================================================
// Special IER functions
uint gmDisableIER( uint mask );
void gmEnableIER( uint mask );
//----------------------------------------------------------------------------
// MX98728 Macronix GMAC Register definitions, ETHC6000F Board
//----------------------------------------------------------------------------
//
// Hardware Reset
//
#define GMAC_RESET_ON (MXBASE+0x10000)
#define GMAC_RESET_OFF (MXBASE+0x20000)
//
// GMAC_CONTROL [ 03 | 02 | 01 | 00 ]
// 00 : NCRA - Network Control Register A
// 01 : NCRB - Network Control Register B
// 02 : TRA - GMAC Test Register A
// 03 : TRB - GMAC Test Register B
//
#define GMAC_CONTROL (MXBASE+0x0)
//
// GMAC_STATS [ 07 | 06 | 05 | 04 ]
// 04 : LTPS - Last Transmitted Packet Status
// 05 : LRPS - Last Received Packet Status
// 07/06 : MPCL - Missed Packet Counter (16bit)
//
#define GMAC_STATS (MXBASE+0x8)
//
// GMAC_ISR [ 0B | 0A | 09 | 08 ]
// 08 : IMR - Interrupt Mask Register
// 09 : IR - Interrupt Register
// 0B/0A : BP - Boundary Page Pointer (16bit)
//
#define GMAC_ISR (MXBASE+0x10)
//
// GMAC_TXRING1 [ 0F | 0E | 0D | 0C ]
// 0D/0C : TLBP - TX Low Boundary Page Pointer (16bit)
// 0F/0E : TWP - TX Write Page Pointer (16bit)
//
#define GMAC_TXRING1 (MXBASE+0x18)
//
// GMAC_TXRING2 [ 13 | 12 | 11 | 10 ]
// 11/10 : RES1 - Reserved (16bit)
// 13/12 : TRP - TX Read Page Pointer (16bit)
//
#define GMAC_TXRING2 (MXBASE+0x20)
//
// GMAC_RXRING1 [ 17 | 16 | 15 | 14 ]
// 15/14 : RXINTT - Receive Interrupt Timer (16bit)
// 17/16 : RWP - Receive Write Page Pointer (16bit)
//
#define GMAC_RXRING1 (MXBASE+0x28)
//
// GMAC_RXRING2 [ 1B | 1A | 19 | 18 ]
// 19/18 : RRP - Receive Read Page Pointer (16bit)
// 1B/1A : RHBP - RX High Boundary Page Pointer (16bit)
//
#define GMAC_RXRING2 (MXBASE+0x30)
//
// GMAC_IORING1 [ 1F | 1E | 1D | 1C ]
// 1C : EEIR - EEPROM Interface Register
// 1D : BICT - Bus Integrity Check Timer
// 1F/1E : IORDP - IO Data Port Page Pointer (16bit)
//
#define GMAC_IORING1 (MXBASE+0x38)
//
// GMAC_ADDR1 [ 23 | 22 | 21 | 20 ]
// 20 : PAR0 - Physical Address Byte 0
// 21 : PAR1 - Physical Address Byte 1
// 22 : PAR2 - Physical Address Byte 2
// 23 : PAR3 - Physical Address Byte 3
//
#define GMAC_ADDR1 (MXBASE+0x40)
//
// GMAC_ADDR2 [ 27 | 26 | 25 | 24 ]
// 24 : PAR4 - Physical Address Byte 4
// 25 : PAR5 - Physical Address Byte 5
// 26 : MAR0 - Hash Table Byte 0
// 27 : MAR1 - Hash Table Byte 1
//
#define GMAC_ADDR2 (MXBASE+0x48)
//
// GMAC_ADDR3 [ 2B | 2A | 29 | 28 ]
// 28 : MAR2 - Hash Table Byte 2
// 29 : MAR3 - Hash Table Byte 3
// 2A : MAR4 - Hash Table Byte 4
// 2B : MAR5 - Hash Table Byte 5
//
#define GMAC_ADDR3 (MXBASE+0x50)
//
// GMAC_ADDR4 [ 2F | 2E | 2D | 2C ]
// 2C : MAR6 - Hash Table Byte 6
// 2D : MAR7 - Hash Table Byte 7
// 2E : ANALOG - Transceiver Control Register
// 2F : DINTVAL - DMA Interval Timer
//
#define GMAC_ADDR4 (MXBASE+0x58)
//
// GMAC_CONFIG [ 33 | 32 | 31 | 30 ]
// 30 : NWAYC - NWAY Configuration Register
// 31 : NWAYS - NWAY Status Register
// 32 : GCA - GMAC Configuration A Register
// 33 : GCB - GMAC Configuration B Register
//
#define GMAC_CONFIG (MXBASE+0x60)
//
// GMAC_TWD [ 37 | 36 | 35 | 34 ]
// 37/34 : TWD - Transmit Write Data Port (32bit)
//
#define GMAC_TWD (MXBASE+0x68)
//
// GMAC_AUX1 [ 3B | 3A | 39 | 38 ]
// 39/38 : RES2 - Reserved (16bit)
// 3A : HIPR - Host Interface Protocol Register
// 3B : LPC - Link Partner Code Register
//
#define GMAC_AUX1 (MXBASE+0x70)
//
// GMAC_AUX2 [ 3F | 3E | 3D | 3C ]
// 3C : DMASR - DMA Status Register
// 3D : MISC1 - MISC Control Register 1
// 3F/3E : TXFIFOCNT - TX FIFO Byte Count Register (16bit)
//
#define GMAC_AUX2 (MXBASE+0x78)
//
// GMAC_RRD [ 43 | 42 | 41 | 40 ]
// 43/40 : RRD - Read Data Port (32bit)
//
#define GMAC_RRD (MXBASE+0x80) // Reg 40h/43h RO
//
// GMAC_ID [ 47 | 46 | 45 | 44 ]
// 45/44 : ID1 - ID Register ('M' << 16 | 'X')
// 47/46 : ID2 - ID Register ("0001")
//
#define GMAC_ID (MXBASE+0x88)
//
// GMAC_WRTXFIFOD [ 4B | 4A | 49 | 48 ]
// 4B/48 : WRTXFIFOD - Write TX FIFO Data Port (32bit)
//
#define GMAC_WRTXFIFOD (MXBASE+0x90) // Reg 48h/4Bh WO
//
// GMAC_IORD [ 4F | 4E | 4D | 4C ]
// 4F/4C : IORD - IO Read Data Port (32bit)
//
#define GMAC_IORD (MXBASE+0x98) // Reg 4Ch/4Fh RO
//
// GMAC_AUX3 [ 53 | 52 | 51 | 50 ]
// 50 : MISC2 - MISC Control Register 2
// 51 : ??? - ???
// 53/52 : HRPKTCNT - Host Receivce Packet Count Register (16bit)
//
#define GMAC_AUX3 (MXBASE+0xA0)
//
// GMAC_FRAGCNT [ 57 | 56 | 55 | 54 ]
// 56/54 : IORD - Host DMA Fragment Counter (24bit)
// 57 : ??? - ???
//
#define GMAC_FRAGCNT (MXBASE+0xA8)
//
//
// GMAC Resiter Field Settings
//
//
// GMAC_CONTROL - NCRA/NCRB/TRA/TRB
#define GM_RESET 0x00000001 // Reset (set, then clear)
#define GM_ST0 0x00000002 // Transmit Command/Status
#define GM_ST1 0x00000004 // ""
#define GM_SR 0x00000008 // Start Receive
#define GM_LB0 0x00000010 // Loopback mode
#define GM_LB1 0x00000020 // ""
#define GM_INTMODE 0x00000040 // Intmode (0=active low)
#define GM_INTCLK 0x00000080 // Must be 0
#define GM_PR 0x00000100 // Promiscuous mode
#define GM_CA 0x00000200 // "Pick-Off" mode when set
#define GM_PM 0x00000400 // Pass all multicast
#define GM_PB 0x00000800 // Pass bad frames
#define GM_AB 0x00001000 // Accept broadcast
#define GM_HBD 0x00002000 // Reserved (set to 0)
#define GM_RXINTC0 0x00004000 // Rx packet INT threshhold
#define GM_RXINTC1 0x00008000 // ""
// GMAC_STATS - LTPS/LRPS/MPCL
#define GM_CC 0x0000000F // Collision count
#define GM_CRSLOST 0x00000010 // Carrier Sense Lost
#define GM_UF 0x00000020 // TX Fifo Underflow
#define GM_OWC 0x00000040 // Out of window collision
#define GM_TERR 0x00000080 // Transmit error
#define GM_BF 0x00000100 // Rx packet buffer full
#define GM_CRC 0x00000200 // Rx packet CRC error
#define GM_FAE 0x00000400 // Frame alignment error
#define GM_FO 0x00000800 // Fifo Overrun
#define GM_RW 0x00001000 // Rx Watchdog
#define GM_MF 0x00002000 // Multicast frame
#define GM_RF 0x00004000 // Runt frame
#define GM_RERR 0x00008000 // Receive Error
// GMAC_ISR - IMR/IR/BP
#define GM_FRAGIM 0x00000001 // Fragment Counter Interrupt
#define GM_RIM 0x00000002 // Rx Interrupt
#define GM_TIM 0x00000004 // Tx Interrupt
#define GM_REIM 0x00000008 // Rx Error Interrupt
#define GM_TEIM 0x00000010 // Tx Error Interrupt
#define GM_FIFOEIM 0x00000020 // Fifo Error Interrupt
#define GM_BUSEIM 0x00000040 // Bus Error Interrupthhold
#define GM_RBFIM 0x00000080 // Rx Buffer Full Interrupt
#define GM_FRAGI 0x00000100 // Fragment Counter Interrupt
#define GM_RI 0x00000200 // Rx Interrupt
#define GM_TI 0x00000400 // Tx Interrupt
#define GM_REI 0x00000800 // Rx Error Interrupt
#define GM_TEI 0x00001000 // Tx Error Interrupt
#define GM_FIFOEI 0x00002000 // Fifo Error Interrupt
#define GM_BUSEI 0x00004000 // Bus Error Interrupthhold
#define GM_RBFI 0x00008000 // Rx Buffer Full Interrupt
// GMAC_CONFIG - NWAYC/NWAYS/GCA/GCB
#define GM_FD 0x00000001 // Full duplex mode
#define GM_PS100 0x00000002 // Port select 100Mb
#define GM_ANE 0x00000004 // Autonegotiate enable
#define GM_ANS0 0x00000008 // Autonegotiate status
#define GM_ANS1 0x00000010 // "
#define GM_ANS2 0x00000020 // "
#define GM_NTTEST 0x00000040 // Res.
#define GM_LTE 0x00000080 // Link test enable (0=force link)
#define GM_LS10 0x00000100 // Link is 10mbs
#define GM_LS100 0x00000200 // Link is 100mbs
#define GM_LPNWAY 0x00000400 // Link partner NWAY
#define GM_ANCLPT 0x00000800 // Autonegotiation complete
#define GM_100TXF 0x00001000 // NWAY 100 FD
#define GM_100TXH 0x00002000 // NWAY 100 HD
#define GM_10TXF 0x00004000 // NWAY 10 FD
#define GM_10TXH 0x00008000 // NWAY 10 HD
#define GM_BPSCRM 0x00010000 // Bypass srambler
#define GM_PBW 0x00020000 // Use 16 bit transfer mode
#define GM_SLOWSRAM 0x00040000 // User slower than 25nS SRAM
#define GM_ARXERRB 0x00080000 // Accept RX packet with error
#define GM_MIISEL 0x00100000 // Use external MII
#define GM_AUTOPUB 0x00200000 //
#define GM_TXFIFOCNTEN 0x00400000 // Enable the use of Tx FIFO cnt regs
#define GM_RES1 0x00800000 // Reserved
#define GM_TTHD0 0x01000000 // Transmit FIFO threshold
#define GM_TTHD1 0x02000000 // "
#define GM_RTHD0 0x04000000 // Receive FIFO threshold
#define GM_RTHD1 0x08000000 // "
// GMAC_AUX1 - RES2/HIPR/LPC
#define GM_WRDYB 0x00010000 // Write packet memory ready
#define GM_RRDYB 0x00020000 // IO Read packet memory ready
#define GM_DREQB 0x00040000 // Rx packet data ready
// GMAC_AUX3 - MISC2/HRPKTCNT
#define GM_HBRLEN0 0x00000001 //
#define GM_HBRLEN1 0x00000002 //
#define GM_RUNTSIZE 0x00000004 // Set to knock runts from 64 to 60
#define GM_DREQBCTRL 0x00000008 // DREQB timing
#define GM_RINTSEL 0x00000010 // Set to IRQ on HOST dma, not local
#define GM_ITPSEL 0x00000020 //
#define GM_A11A8EN 0x00000040 //
#define GM_AUTORCVR 0x00000080 // Set to enable autorecover on rx dma
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