📄 csl_emachal.h
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\******************************************************************************/
#define _EMAC_MACADDRM_ADDR (_EMAC_BASE_ADDR+0x01D0u)
#define EMAC_MACADDRM EMAC_REG(MACADDRM)
#define _EMAC_MACADDRM_MACADDR8_MASK 0x000000FFu
#define _EMAC_MACADDRM_MACADDR8_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | MACADDRH |
* |___________________|
*
* MACADDRH - MAC Address High Bytes Register (bits 47:16)
*
* FIELDS (msb -> lsb)
* (rw) MACADDR32 - 32 bits of MAC Address
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI .
* EMAC_RSETI .
* EMAC_FGETI .
* EMAC_FSETI .
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_MACADDRH_ADDR (_EMAC_BASE_ADDR+0x01D4u)
#define EMAC_MACADDRH EMAC_REG(MACADDRH)
#define _EMAC_MACADDRH_MACADDR32_MASK 0xFFFFFFFFu
#define _EMAC_MACADDRH_MACADDR32_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | MACHASH1 |
* | MACHASH2 |
* |___________________|
*
* MACHASH1 - MAC Address Hash 1 Register
* MACHASH2 - MAC Address Hash 2 Register
*
* FIELDS (msb -> lsb)
* (rw) HASHBITS - 32 Hash Bits
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI .
* EMAC_RSETI .
* EMAC_FGETI .
* EMAC_FSETI .
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_MACHASH1_ADDR (_EMAC_BASE_ADDR+0x01D8u)
#define _EMAC_MACHASH2_ADDR (_EMAC_BASE_ADDR+0x01DCu)
#define EMAC_MACHASH1 EMAC_REG(MACHASH1)
#define EMAC_MACHASH2 EMAC_REG(MACHASH2)
#define _EMAC_MACHASH1_HASHBITS_MASK 0xFFFFFFFFu
#define _EMAC_MACHASH1_HASHBITS_SHIFT 0u
#define _EMAC_MACHASH2_HASHBITS_MASK 0xFFFFFFFFu
#define _EMAC_MACHASH2_HASHBITS_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | BOFFTEST |
* |___________________|
*
* BOFFTEST - Backoff Test Register
*
* FIELDS (msb -> lsb)
* (rw) BOFFHALT - Halt Random Number Generator
* (rw) ATTEMPT - Initial Collision Attempt Count
* (rw) BOFFRNG - Backoff Random Number Generator
* (rw) RETRYCOUNT - Retry Count
* (rw) BOFFCOUNT - Backoff Current Count
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI .
* EMAC_RSETI .
* EMAC_FGETI .
* EMAC_FSETI .
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_BOFFTEST_ADDR (_EMAC_BASE_ADDR+0x01E0u)
#define EMAC_BOFFTEST EMAC_REG(BOFFTEST)
#define _EMAC_BOFFTEST_BOFFHALT_MASK 0x8000000u
#define _EMAC_BOFFTEST_BOFFHALT_SHIFT 31u
#define _EMAC_BOFFTEST_ATTEMPT_MASK 0x78000000u
#define _EMAC_BOFFTEST_ATTEMPT_SHIFT 27u
#define _EMAC_BOFFTEST_BOFFRNG_MASK 0x07FF0000u
#define _EMAC_BOFFTEST_BOFFRNG_SHIFT 16u
#define _EMAC_BOFFTEST_RETRYCOUNT_MASK 0x0000F000u
#define _EMAC_BOFFTEST_RETRYCOUNT_SHIFT 12u
#define _EMAC_BOFFTEST_BOFFCOUNT_MASK 0x000003FFu
#define _EMAC_BOFFTEST_BOFFCOUNT_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | TPACETEST |
* |___________________|
*
* TPACETEST - Transmit Pacing Test Register
*
* FIELDS (msb -> lsb)
* (rw) PACEVAL - Pace Register Current Value
* (rw) PACEINIT - Pace Register Initial Value
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI .
* EMAC_RSETI .
* EMAC_FGETI .
* EMAC_FSETI .
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_TPACETEST_ADDR (_EMAC_BASE_ADDR+0x01E4u)
#define EMAC_TPACETEST EMAC_REG(TPACETEST)
#define _EMAC_TPACETEST_PACEVAL_MASK 0x0000001Fu
#define _EMAC_TPACETEST_PACEVAL_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | RXPAUSE |
* | TXPAUSE |
* |___________________|
*
* RXPAUSE - Receive Pause Timer Register
* TXPAUSE - Transmit Pause Timer Register
*
* FIELDS (msb -> lsb)
* (rw) PAUSETIMER - Pause Timer
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI .
* EMAC_RSETI .
* EMAC_FGETI .
* EMAC_FSETI .
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_RXPAUSE_ADDR (_EMAC_BASE_ADDR+0x01E8u)
#define _EMAC_TXPAUSE_ADDR (_EMAC_BASE_ADDR+0x01ECu)
#define EMAC_RXPAUSE EMAC_REG(RXPAUSE)
#define EMAC_TXPAUSE EMAC_REG(TXPAUSE)
#define _EMAC_RXPAUSE_PAUSETIMER_MASK 0x0000FFFFu
#define _EMAC_RXPAUSE_PAUSETIMER_SHIFT 0u
#define _EMAC_TXPAUSE_PAUSETIMER_MASK 0x0000FFFFu
#define _EMAC_TXPAUSE_PAUSETIMER_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | TXHDP |
* | TXnHDP |
* |___________________|
*
* TXHDP - TX DMA Head Descriptor Pointer Register for RSETI/RGETI
* TX0HDP - TX Channel 0 DMA Head Descriptor Pointer Register
* TX1HDP - TX Channel 1 DMA Head Descriptor Pointer Register
* TX2HDP - TX Channel 2 DMA Head Descriptor Pointer Register
* TX3HDP - TX Channel 3 DMA Head Descriptor Pointer Register
* TX4HDP - TX Channel 4 DMA Head Descriptor Pointer Register
* TX5HDP - TX Channel 5 DMA Head Descriptor Pointer Register
* TX6HDP - TX Channel 6 DMA Head Descriptor Pointer Register
* TX7HDP - TX Channel 7 DMA Head Descriptor Pointer Register
*
* FIELDS (msb -> lsb)
* (rw) DESCPTR - Descriptor Pointer
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI y
* EMAC_RSETI y
* EMAC_FGETI y
* EMAC_FSETI y
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_TXHDP_BASEADDR (_EMAC_BASE_ADDR+0x0600u)
#define _EMAC_TX0HDP_ADDR (_EMAC_BASE_ADDR+0x0600u)
#define _EMAC_TX1HDP_ADDR (_EMAC_BASE_ADDR+0x0604u)
#define _EMAC_TX2HDP_ADDR (_EMAC_BASE_ADDR+0x0608u)
#define _EMAC_TX3HDP_ADDR (_EMAC_BASE_ADDR+0x060Cu)
#define _EMAC_TX4HDP_ADDR (_EMAC_BASE_ADDR+0x0610u)
#define _EMAC_TX5HDP_ADDR (_EMAC_BASE_ADDR+0x0614u)
#define _EMAC_TX6HDP_ADDR (_EMAC_BASE_ADDR+0x0618u)
#define _EMAC_TX7HDP_ADDR (_EMAC_BASE_ADDR+0x061Cu)
#define EMAC_TX0HDP EMAC_REG(TX0HDP)
#define EMAC_TX1HDP EMAC_REG(TX1HDP)
#define EMAC_TX2HDP EMAC_REG(TX2HDP)
#define EMAC_TX3HDP EMAC_REG(TX3HDP)
#define EMAC_TX4HDP EMAC_REG(TX4HDP)
#define EMAC_TX5HDP EMAC_REG(TX5HDP)
#define EMAC_TX6HDP EMAC_REG(TX6HDP)
#define EMAC_TX7HDP EMAC_REG(TX7HDP)
#define _EMAC_TXHDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TXHDP_DESCPTR_SHIFT 0u
#define _EMAC_TX0HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX0HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX1HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX1HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX2HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX2HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX3HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX3HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX4HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX4HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX5HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX5HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX6HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX6HDP_DESCPTR_SHIFT 0u
#define _EMAC_TX7HDP_DESCPTR_MASK 0xFFFFFFFFu
#define _EMAC_TX7HDP_DESCPTR_SHIFT 0u
/******************************************************************************\
* _____________________
* | |
* | RXHDP |
* | RXnHDP |
* |___________________|
*
* RXHDP - RX DMA Head Descriptor Pointer Register for RSETI/RGETI
* RX0HDP - RX Channel 0 DMA Head Descriptor Pointer Register
* RX1HDP - RX Channel 1 DMA Head Descriptor Pointer Register
* RX2HDP - RX Channel 2 DMA Head Descriptor Pointer Register
* RX3HDP - RX Channel 3 DMA Head Descriptor Pointer Register
* RX4HDP - RX Channel 4 DMA Head Descriptor Pointer Register
* RX5HDP - RX Channel 5 DMA Head Descriptor Pointer Register
* RX6HDP - RX Channel 6 DMA Head Descriptor Pointer Register
* RX7HDP - RX Channel 7 DMA Head Descriptor Pointer Register
*
* FIELDS (msb -> lsb)
* (rw) DESCPTR - Descriptor Pointer
*
* MACROS SUPPORTED
* EMAC_FMK y
* EMAC_FMKS .
* EMAC_FMKCHF .
* EMAC_ADDR y
* EMAC_REG y
* EMAC_RGET y
* EMAC_RSET y
* EMAC_FGET y
* EMAC_FSET y
* EMAC_FSETS .
* EMAC_RGETI y
* EMAC_RSETI y
* EMAC_FGETI y
* EMAC_FSETI y
* EMAC_FSETSI .
*
\******************************************************************************/
#define _EMAC_RXHDP_BASEADDR (_EMAC_BASE_ADDR+0x0620u)
#define _EMAC_RX0HDP_ADDR (_EMAC_BASE_ADDR+0x0620u)
#define _EMAC_RX1HDP_ADDR (_EMAC_BASE_ADDR+0x0624u)
#define _EMAC_RX2HDP_ADDR (_EMAC_BASE_ADDR+0x0628u)
#define _EMAC_RX3HDP_ADDR (_EMAC_BASE_ADDR+0x062Cu)
#define _EMAC_RX4HDP_ADDR (_EMAC_BASE_ADDR+0x0630u)
#define _EMAC_RX5HDP_ADDR (_EMAC_BASE_ADDR+0x0634u)
#define _EMAC_RX6HDP_ADDR (_EMAC_BASE_ADDR+0x0638u)
#define _EMAC_RX7HDP_ADDR (_EMAC_BASE_ADDR+0x063Cu)
#define EMAC_RX0HDP EMAC_REG(RX0HDP)
#define EMAC_RX1HDP EMAC_REG(RX1HDP)
#define EMAC_RX2HDP EMAC_REG(RX2HDP)
#define EMAC_RX3HDP EMAC_REG(RX3HDP)
#define EMAC_RX4HDP EMAC_REG(RX4HDP)
#define EMAC_RX5HDP EMAC_REG(RX5HDP)
#define EMAC_RX6HDP EMAC_REG(RX6HDP)
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