csl_emachal.h

dm642网络传输程序

*  EMAC_FSET    y
*  EMAC_FSETS   .
*  EMAC_RGETI   .
*  EMAC_RSETI   .
*  EMAC_FGETI   .
*  EMAC_FSETI   .
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_RXBUFFEROFFSET_ADDR               (_EMAC_BASE_ADDR+0x0110u)

#define EMAC_RXBUFFEROFFSET                     EMAC_REG(RXBUFFEROFFSET)

#define _EMAC_RXBUFFEROFFSET_BUFFEROFFSET_MASK  0x0000FFFFu
#define _EMAC_RXBUFFEROFFSET_BUFFEROFFSET_SHIFT 0u



/******************************************************************************\
* _____________________
* |                   |
* | RXFILTERLOWTHRESH |
* |___________________|
*
* RXFILTERLOWTHRESH - RX Filer Low Priority Packets Threshhold
*
* FIELDS (msb -> lsb)
*  (rw)  FILTERTHRESH
*
* MACROS SUPPORTED
*  EMAC_FMK     y
*  EMAC_FMKS    .
*  EMAC_FMKCHF  .
*  EMAC_ADDR    y
*  EMAC_REG     y
*  EMAC_RGET    y
*  EMAC_RSET    y
*  EMAC_FGET    y
*  EMAC_FSET    y
*  EMAC_FSETS   .
*  EMAC_RGETI   .
*  EMAC_RSETI   .
*  EMAC_FGETI   .
*  EMAC_FSETI   .
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_RXFILTERLOWTHRESH_ADDR            (_EMAC_BASE_ADDR+0x0114u)

#define EMAC_RXFILTERLOWTHRESH                  EMAC_REG(RXFILTERLOWTHRESH)

#define _EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_MASK    0x000000FFu
#define _EMAC_RXFILTERLOWTHRESH_FILTERTHRESH_SHIFT   0u



/******************************************************************************\
* _____________________
* |                   |
* |   RXFLOWTHRESH    |
* |   RXnFLOWTHRESH   |
* |___________________|
*
* RXFLOWTHRESH      - RX Flow Control Threshhold for RSETI/RGETI
* RX0FLOWTHRESH     - RX Channel 0 Flow Control Threshhold
* RX1FLOWTHRESH     - RX Channel 1 Flow Control Threshhold
* RX2FLOWTHRESH     - RX Channel 2 Flow Control Threshhold
* RX3FLOWTHRESH     - RX Channel 3 Flow Control Threshhold
* RX4FLOWTHRESH     - RX Channel 4 Flow Control Threshhold
* RX5FLOWTHRESH     - RX Channel 5 Flow Control Threshhold
* RX6FLOWTHRESH     - RX Channel 6 Flow Control Threshhold
* RX7FLOWTHRESH     - RX Channel 7 Flow Control Threshhold
*
* FIELDS (msb -> lsb)
*  (rw)  FLOWTHRESH
*
* MACROS SUPPORTED
*  EMAC_FMK     y
*  EMAC_FMKS    .
*  EMAC_FMKCHF  .
*  EMAC_ADDR    y
*  EMAC_REG     y
*  EMAC_RGET    y
*  EMAC_RSET    y
*  EMAC_FGET    y
*  EMAC_FSET    y
*  EMAC_FSETS   .
*  EMAC_RGETI   y
*  EMAC_RSETI   y
*  EMAC_FGETI   y
*  EMAC_FSETI   y
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_RXFLOWTHRESH_BASEADDR             (_EMAC_BASE_ADDR+0x0120u)
#define _EMAC_RX0FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0120u)
#define _EMAC_RX1FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0124u)
#define _EMAC_RX2FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0128u)
#define _EMAC_RX3FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x012Cu)
#define _EMAC_RX4FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0130u)
#define _EMAC_RX5FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0134u)
#define _EMAC_RX6FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x0138u)
#define _EMAC_RX7FLOWTHRESH_ADDR                (_EMAC_BASE_ADDR+0x013Cu)

#define EMAC_RX0FLOWTHRESH                      EMAC_REG(RX0FLOWTHRESH)
#define EMAC_RX1FLOWTHRESH                      EMAC_REG(RX1FLOWTHRESH)
#define EMAC_RX2FLOWTHRESH                      EMAC_REG(RX2FLOWTHRESH)
#define EMAC_RX3FLOWTHRESH                      EMAC_REG(RX3FLOWTHRESH)
#define EMAC_RX4FLOWTHRESH                      EMAC_REG(RX4FLOWTHRESH)
#define EMAC_RX5FLOWTHRESH                      EMAC_REG(RX5FLOWTHRESH)
#define EMAC_RX6FLOWTHRESH                      EMAC_REG(RX6FLOWTHRESH)
#define EMAC_RX7FLOWTHRESH                      EMAC_REG(RX7FLOWTHRESH)

#define _EMAC_RXFLOWTHRESH_FLOWTHRESH_MASK      0x000000FFu
#define _EMAC_RXFLOWTHRESH_FLOWTHRESH_SHIFT     0u
#define _EMAC_RX0FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX0FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX1FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX1FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX2FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX2FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX3FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX3FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX4FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX4FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX5FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX5FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX6FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX6FLOWTHRESH_FLOWTHRESH_SHIFT    0u
#define _EMAC_RX7FLOWTHRESH_FLOWTHRESH_MASK     0x000000FFu
#define _EMAC_RX7FLOWTHRESH_FLOWTHRESH_SHIFT    0u



/******************************************************************************\
* _____________________
* |                   |
* |   RXFREEBUFFER    |
* |   RXnFREEBUFFER   |
* |___________________|
*
* RXFREEBUFFER      - RX Free Buffer Count for RSETI/RGETI
* RX0FREEBUFFER     - RX Channel 0 Free Buffer Count Register
* RX1FREEBUFFER     - RX Channel 1 Free Buffer Count Register
* RX2FREEBUFFER     - RX Channel 2 Free Buffer Count Register
* RX3FREEBUFFER     - RX Channel 3 Free Buffer Count Register
* RX4FREEBUFFER     - RX Channel 4 Free Buffer Count Register
* RX5FREEBUFFER     - RX Channel 5 Free Buffer Count Register
* RX6FREEBUFFER     - RX Channel 6 Free Buffer Count Register
* RX7FREEBUFFER     - RX Channel 7 Free Buffer Count Register
*
* FIELDS (msb -> lsb)
*  (rw)  FREEBUF
*
* MACROS SUPPORTED
*  EMAC_FMK     y
*  EMAC_FMKS    .
*  EMAC_FMKCHF  .
*  EMAC_ADDR    y
*  EMAC_REG     y
*  EMAC_RGET    y
*  EMAC_RSET    y
*  EMAC_FGET    y
*  EMAC_FSET    y
*  EMAC_FSETS   .
*  EMAC_RGETI   y
*  EMAC_RSETI   y
*  EMAC_FGETI   y
*  EMAC_FSETI   y
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_RXFREEBUFFER_BASEADDR             (_EMAC_BASE_ADDR+0x0140u)
#define _EMAC_RX0FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0140u)
#define _EMAC_RX1FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0144u)
#define _EMAC_RX2FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0148u)
#define _EMAC_RX3FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x014Cu)
#define _EMAC_RX4FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0150u)
#define _EMAC_RX5FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0154u)
#define _EMAC_RX6FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x0158u)
#define _EMAC_RX7FREEBUFFER_ADDR                (_EMAC_BASE_ADDR+0x015Cu)

#define EMAC_RX0FREEBUFFER                      EMAC_REG(RX0FREEBUFFER)
#define EMAC_RX1FREEBUFFER                      EMAC_REG(RX1FREEBUFFER)
#define EMAC_RX2FREEBUFFER                      EMAC_REG(RX2FREEBUFFER)
#define EMAC_RX3FREEBUFFER                      EMAC_REG(RX3FREEBUFFER)
#define EMAC_RX4FREEBUFFER                      EMAC_REG(RX4FREEBUFFER)
#define EMAC_RX5FREEBUFFER                      EMAC_REG(RX5FREEBUFFER)
#define EMAC_RX6FREEBUFFER                      EMAC_REG(RX6FREEBUFFER)
#define EMAC_RX7FREEBUFFER                      EMAC_REG(RX7FREEBUFFER)

#define _EMAC_RXFREEBUFFER_FREEBUF_MASK         0x0000FFFFu
#define _EMAC_RXFREEBUFFER_FREEBUF_SHIFT        0u
#define _EMAC_RX0FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX0FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX1FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX1FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX2FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX2FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX3FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX3FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX4FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX4FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX5FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX5FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX6FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX6FREEBUFFER_FREEBUF_SHIFT       0u
#define _EMAC_RX7FREEBUFFER_FREEBUF_MASK        0x0000FFFFu
#define _EMAC_RX7FREEBUFFER_FREEBUF_SHIFT       0u



/******************************************************************************\
* _____________________
* |                   |
* |   MACCONTROL      |
* |___________________|
*
* MACCONTROL        - MAC Control Register
*
* FIELDS (msb -> lsb)
* (rw)  TXPTYPE     - TX Priority Queue Type
* (rw)  TXPACE      - TX Pacing Enable
* (rw)  MIIEN       - MII Enable
* (rw)  TXFLOWEN    - TX Flow Control Enable
* (rw)  RXFLOWEN    - RX Flow Control Enable
* (rw)  MTEST       - Manufacturer's Test Enable
* (rw)  LOOPBACK    - Loopback Mode Enable
* (rw)  FULLDUPLEX  - Full Duplex Mode Enable
*
* MACROS SUPPORTED
*  EMAC_FMK     y
*  EMAC_FMKS    y
*  EMAC_FMKCHF  .
*  EMAC_ADDR    y
*  EMAC_REG     y
*  EMAC_RGET    y
*  EMAC_RSET    y
*  EMAC_FGET    y
*  EMAC_FSET    y
*  EMAC_FSETS   y
*  EMAC_RGETI   .
*  EMAC_RSETI   .
*  EMAC_FGETI   .
*  EMAC_FSETI   .
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_MACCONTROL_ADDR                   (_EMAC_BASE_ADDR+0x0160u)

#define EMAC_MACCONTROL                         EMAC_REG(MACCONTROL)

#define _EMAC_MACCONTROL_TXPTYPE_MASK           0x00000200u
#define _EMAC_MACCONTROL_TXPTYPE_SHIFT          9u
#define EMAC_MACCONTROL_TXPTYPE_RROBIN          0u
#define EMAC_MACCONTROL_TXPTYPE_CHANNELPRI      1u

#define _EMAC_MACCONTROL_TXPACE_MASK            0x00000040u
#define _EMAC_MACCONTROL_TXPACE_SHIFT           6u
#define EMAC_MACCONTROL_TXPACE_DISABLE          0u
#define EMAC_MACCONTROL_TXPACE_ENABLE           1u

#define _EMAC_MACCONTROL_MIIEN_MASK             0x00000020u
#define _EMAC_MACCONTROL_MIIEN_SHIFT            5u
#define EMAC_MACCONTROL_MIIEN_DISABLE           0u
#define EMAC_MACCONTROL_MIIEN_ENABLE            1u

#define _EMAC_MACCONTROL_TXFLOWEN_MASK          0x00000010u
#define _EMAC_MACCONTROL_TXFLOWEN_SHIFT         4u
#define EMAC_MACCONTROL_TXFLOWEN_DISABLE        0u
#define EMAC_MACCONTROL_TXFLOWEN_ENABLE         1u

#define _EMAC_MACCONTROL_RXFLOWEN_MASK          0x00000008u
#define _EMAC_MACCONTROL_RXFLOWEN_SHIFT         3u
#define EMAC_MACCONTROL_RXFLOWEN_DISABLE        0u
#define EMAC_MACCONTROL_RXFLOWEN_ENABLE         1u

#define _EMAC_MACCONTROL_MTEST_MASK             0x00000004u
#define _EMAC_MACCONTROL_MTEST_SHIFT            2u
#define EMAC_MACCONTROL_MTEST_DISABLE           0u
#define EMAC_MACCONTROL_MTEST_ENABLE            1u

#define _EMAC_MACCONTROL_LOOPBACK_MASK          0x00000002u
#define _EMAC_MACCONTROL_LOOPBACK_SHIFT         1u
#define EMAC_MACCONTROL_LOOPBACK_DISABLE        0u
#define EMAC_MACCONTROL_LOOPBACK_ENABLE         1u

#define _EMAC_MACCONTROL_FULLDUPLEX_MASK        0x00000001u
#define _EMAC_MACCONTROL_FULLDUPLEX_SHIFT       0u
#define EMAC_MACCONTROL_FULLDUPLEX_DISABLE      0u
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE       1u



/******************************************************************************\
* _____________________
* |                   |
* |   MACSTATUS       |
* |___________________|
*
* MACSTATUS         - MAC Status Register
*
* FIELDS (msb -> lsb)
* (r)  TXERRCODE    - TX Host Error Code
* (r)  THERRCH      - TX Host Error Channel
* (r)  RXERRCODE    - RX Host Error Code
* (r)  RXERRCH      - RX Host Error Channel
* (r)  RXQOSACT     - RX QOS Service Currently Active
* (r)  RXFLOWACT    - RX Flow Control Currently Active
* (r)  TXFLOWACT    - TX Flow Control Currently Active
*
* MACROS SUPPORTED
*  EMAC_FMK     y
*  EMAC_FMKS    y
*  EMAC_FMKCHF  .
*  EMAC_ADDR    y
*  EMAC_REG     y
*  EMAC_RGET    y
*  EMAC_RSET    y
*  EMAC_FGET    y
*  EMAC_FSET    y
*  EMAC_FSETS   y
*  EMAC_RGETI   .
*  EMAC_RSETI   .
*  EMAC_FGETI   .
*  EMAC_FSETI   .
*  EMAC_FSETSI  .
*
\******************************************************************************/
#define _EMAC_MACSTATUS_ADDR                    (_EMAC_BASE_ADDR+0x0164u)

#define EMAC_MACSTATUS                          EMAC_REG(MACSTATUS)

#define _EMAC_MACSTATUS_TXERRCODE_MASK          0x00F00000u
#define _EMAC_MACSTATUS_TXERRCODE_SHIFT         20u
#define EMAC_MACSTATUS_TXERRCODE_NOERROR        0u
#define EMAC_MACSTATUS_TXERRCODE_SOPERROR       1u
#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP      2u
#define EMAC_MACSTATUS_TXERRCODE_NOEOP          3u
#define EMAC_MACSTATUS_TXERRCODE_NULLPTR        4u
#define EMAC_MACSTATUS_TXERRCODE_NULLLEN        5u
#define EMAC_MACSTATUS_TXERRCODE_LENRRROR       6u

#define _EMAC_MACSTATUS_TXERRCH_MASK            0x00070000u
#define _EMAC_MACSTATUS_TXERRCH_SHIFT           16u

#define _EMAC_MACSTATUS_RXERRCODE_MASK          0x0000F000u
#define _EMAC_MACSTATUS_RXERRCODE_SHIFT         12u
#define EMAC_MACSTATUS_RXERRCODE_NOERROR        0u
#define EMAC_MACSTATUS_RXERRCODE_SOPERROR       1u
#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP      2u
#define EMAC_MACSTATUS_RXERRCODE_NOEOP          3u
#define EMAC_MACSTATUS_RXERRCODE_NULLPTR        4u
#define EMAC_MACSTATUS_RXERRCODE_NULLLEN        5u
#define EMAC_MACSTATUS_RXERRCODE_LENRRROR       6u

#define _EMAC_MACSTATUS_RXERRCH_MASK            0x00000700u
#define _EMAC_MACSTATUS_RXERRCH_SHIFT           8u

#define _EMAC_MACSTATUS_RXQOSACT_MASK           0x00000004u
#define _EMAC_MACSTATUS_RXQOSACT_SHIFT          2u

#define _EMAC_MACSTATUS_RXFLOWACT_MASK          0x00000002u
#define _EMAC_MACSTATUS_RXFLOWACT_SHIFT         1u

#define _EMAC_MACSTATUS_TXFLOWACT_MASK          0x00000001u