xsimtestbench_arch.cpp

用ISE开发的VHDL随机地址发生器,采用循环计数生成地址

#include "isim/work/tcntl_tb/testbench_arch.h"
#include "isim/work/glbl/glbl.h"
static const char * HSimCopyRightNotice = "Copyright 2004-2005, Xilinx Inc. All rights reserved.";
#include "E:/Xilinx/vhdl/hdp/nt/ieee/std_logic_1164/std_logic_1164.h"
#include "E:/Xilinx/vhdl/hdp/nt/ieee/std_logic_arith/std_logic_arith.h"
#include "E:/Xilinx/vhdl/hdp/nt/std/textio/textio.h"
#include "E:/Xilinx/vhdl/hdp/nt/ieee/std_logic_unsigned/std_logic_unsigned.h"
#include "E:/Xilinx/vhdl/hdp/nt/ieee/std_logic_textio/std_logic_textio.h"


#include "simprim_ver.auxlib/ffsrce/ffsrce.h"
static HSim__s6* IF0(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibMffsrce(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___b_u_f/_x___b_u_f.h"
static HSim__s6* IF1(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___b_u_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___b_u_f_g_m_u_x/_x___b_u_f_g_m_u_x.h"
static HSim__s6* IF2(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___b_u_f_g_m_u_x(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___f_f/_x___f_f.h"
static HSim__s6* IF3(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___f_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___f_f/_x___f_f.h"
static HSim__s6* IF4(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___f_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___i_n_v/_x___i_n_v.h"
static HSim__s6* IF5(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___i_n_v(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___i_p_a_d/_x___i_p_a_d.h"
static HSim__s6* IF6(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___i_p_a_d(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___l_u_t4/_x___l_u_t4.h"
static HSim__s6* IF7(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___l_u_t4(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_b_u_f/_x___o_b_u_f.h"
static HSim__s6* IF8(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_b_u_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_n_e/_x___o_n_e.h"
static HSim__s6* IF9(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_n_e(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_p_a_d/_x___o_p_a_d.h"
static HSim__s6* IF10(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_p_a_d(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___z_e_r_o/_x___z_e_r_o.h"
static HSim__s6* IF11(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___z_e_r_o(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___z_e_r_o/_x___z_e_r_o.h"
static HSim__s6* IF12(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___z_e_r_o(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_p_a_d/_x___o_p_a_d.h"
static HSim__s6* IF13(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_p_a_d(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_n_e/_x___o_n_e.h"
static HSim__s6* IF14(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_n_e(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___o_b_u_f/_x___o_b_u_f.h"
static HSim__s6* IF15(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___o_b_u_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___l_u_t4/_x___l_u_t4.h"
static HSim__s6* IF16(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___l_u_t4(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___i_p_a_d/_x___i_p_a_d.h"
static HSim__s6* IF17(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___i_p_a_d(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___i_n_v/_x___i_n_v.h"
static HSim__s6* IF18(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___i_n_v(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___f_f/_x___f_f.h"
static HSim__s6* IF19(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___f_f(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___b_u_f_g_m_u_x/_x___b_u_f_g_m_u_x.h"
static HSim__s6* IF20(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___b_u_f_g_m_u_x(label); 
    return blk;
}


#include "simprim_ver.auxlib/_x___b_u_f/_x___b_u_f.h"
static HSim__s6* IF21(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new simprim_ver_auxlibM_x___b_u_f(label); 
    return blk;
}


#include "work/_t_c_n_t_l/_t_c_n_t_l.h"
static HSim__s6* IF22(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workM_t_c_n_t_l(label); 
    return blk;
}


#include "work/glbl/glbl.h"
static HSim__s6* IF23(HSim__s6 *Arch,const char* label,int nGenerics, 
va_list vap)
{
    HSim__s6 *blk = new workMglbl(label); 
    return blk;
}

class _top : public HSim__s6 {
public:
    _top() : HSim__s6(false, "_top", "_top", 0, 0, HSim::VerilogModule) {}
    HSimConfigDecl * topModuleInstantiate() {
        HSimConfigDecl * cfgvh = 0;
        cfgvh = new HSimConfigDecl("default");
        (*cfgvh).addVlogModule("ffsrce", (HSimInstFactoryPtr)IF0);
        (*cfgvh).addVlogModule("X_BUF", (HSimInstFactoryPtr)IF1);
        (*cfgvh).addVlogModule("X_BUFGMUX", (HSimInstFactoryPtr)IF2);
        (*cfgvh).addVlogModule("X_FF", (HSimInstFactoryPtr)IF3);
        (*cfgvh).addVlogModule("X_FF", (HSimInstFactoryPtr)IF4);
        (*cfgvh).addVlogModule("X_INV", (HSimInstFactoryPtr)IF5);
        (*cfgvh).addVlogModule("X_IPAD", (HSimInstFactoryPtr)IF6);
        (*cfgvh).addVlogModule("X_LUT4", (HSimInstFactoryPtr)IF7);
        (*cfgvh).addVlogModule("X_OBUF", (HSimInstFactoryPtr)IF8);
        (*cfgvh).addVlogModule("X_ONE", (HSimInstFactoryPtr)IF9);
        (*cfgvh).addVlogModule("X_OPAD", (HSimInstFactoryPtr)IF10);
        (*cfgvh).addVlogModule("X_ZERO", (HSimInstFactoryPtr)IF11);
        (*cfgvh).addVlogModule("X_ZERO", (HSimInstFactoryPtr)IF12);
        (*cfgvh).addVlogModule("X_OPAD", (HSimInstFactoryPtr)IF13);
        (*cfgvh).addVlogModule("X_ONE", (HSimInstFactoryPtr)IF14);
        (*cfgvh).addVlogModule("X_OBUF", (HSimInstFactoryPtr)IF15);
        (*cfgvh).addVlogModule("X_LUT4", (HSimInstFactoryPtr)IF16);
        (*cfgvh).addVlogModule("X_IPAD", (HSimInstFactoryPtr)IF17);
        (*cfgvh).addVlogModule("X_INV", (HSimInstFactoryPtr)IF18);
        (*cfgvh).addVlogModule("X_FF", (HSimInstFactoryPtr)IF19);
        (*cfgvh).addVlogModule("X_BUFGMUX", (HSimInstFactoryPtr)IF20);
        (*cfgvh).addVlogModule("X_BUF", (HSimInstFactoryPtr)IF21);
        (*cfgvh).addVlogModule("TCNTL", (HSimInstFactoryPtr)IF22);
        (*cfgvh).addVlogModule("glbl", (HSimInstFactoryPtr)IF23);
        HSim__s6 * topvh = 0;
        topvh = new Work_tcntl_tb_testbench_arch("TCNTL_tb");
        addChild(topvh);
        HSim__s5 * topvl = 0;
        topvl = new workMglbl("glbl");
        topvl->moduleInstantiate(cfgvh);
        addChild(topvl);
        return cfgvh;
}
};

main(int argc, char **argv) {
  HSimDesign::initDesign();
  globalKernel->getOptions(argc,argv);
  HSim__s6 * _top_i = 0;
  try {
    IeeeStd_logic_1164=new Ieee_std_logic_1164("Std_logic_1164");
    IeeeStd_logic_arith=new Ieee_std_logic_arith("Std_logic_arith");
    StdTextio=new Std_textio("Textio");
    IeeeStd_logic_unsigned=new Ieee_std_logic_unsigned("Std_logic_unsigned");
    IeeeStd_logic_textio=new Ieee_std_logic_textio("Std_logic_textio");
    HSimConfigDecl *cfg;
 _top_i = new _top();
  cfg =  _top_i->topModuleInstantiate();
    return globalKernel->runTcl(cfg, _top_i, "_top", argc, argv);
  }
  catch (HSimError& msg){
    try {
      globalKernel->error(msg.ErrMsg);
      return 1;
    }
    catch(...) {}
      return 1;
  }
  catch (...){
    globalKernel->fatalError();
    return 1;
  }
}