2410init.s

2410 boot loader,usb ftp

	
	;Copy and paste RW data/zero initialized data
	ldr	r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
;	ldr r2, =|Image$$RO$$Base|
;	add r0, r0, r2
	ldr	r1, =|Image$$RW$$Base|  ; and RAM copy
	ldr	r3, =|Image$$ZI$$Base|  
	
	;Zero init base => top of initialised data
	cmp	r0, r1      ; Check that they are different
	beq	%F2
1       
	cmp	r1, r3      ; Copy init data
	ldrcc	r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4         
	strcc	r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
	bcc	%B1
2       
	ldr	r1, =|Image$$ZI$$Limit| ; Top of zero init segment
	mov	r2, #0
3       
	cmp	r3, r1      ; Zero init
	strcc	r2, [r3], #4
	bcc	%B3

          
    [ :LNOT:THUMBCODE
    	bl	Main        ;Don't use main() because ......
    	b	.                       
    ]

    [ THUMBCODE         ;for start-up code for Thumb mode
    	orr	lr,pc,#1
    	bx	lr
    	CODE16
    	bl	Main        ;Don't use main() because ......
    	b	.
    	CODE32
    ]

;function initializing stacks
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1		;UndefMode
	ldr	sp,=UndefStack
	
	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		;AbortMode
	ldr	sp,=AbortStack

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack
    
	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		;FIQMode
	ldr	sp,=FIQStack

	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode
	ldr	sp,=SVCStack
	
	;USER mode has not be initialized.
	
	mov	pc,lr 
	;The LR register won't be valid if the current mode is not SVC mode.


	LTORG




NAND_CTL_BASE	EQU	0x4e000000
oNFCONF			EQU	0x00
oNFCMD			EQU	0x04
oNFSTAT			EQU	0x10
;
; copy_myself: copy bootloader to ram
;
;void copy_myself(void)
   EXPORT copy_myself
copy_myself
	mov	r10, lr

	; reset NAND
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =0xf830		; initial value
	str	r2, [r1, #oNFCONF]
	ldr	r2, [r1, #oNFCONF]
	bic	r2, r2, #0x800		; enable chip
	str	r2, [r1, #oNFCONF]
	mov	r2, #0xff		; RESET command
	strb	r2, [r1, #oNFCMD]
	mov	r3, #0			; wait 
1	add	r3, r3, #0x1
	cmp	r3, #0xa
	blt	%B1
2	ldr	r2, [r1, #oNFSTAT]	; wait ready
	tst	r2, #0x1
	beq	%B2
	ldr	r2, [r1, #oNFCONF]
	orr	r2, r2, #0x800		; disable chip
	str	r2, [r1, #oNFCONF]

	; get read to call C functions (for nand_read())
	;ldr	sp, DW_STACK_START	; setup stack pointer
	ldr sp, =SVCStack
	mov	fp, #0			; no previous frame, so fp=0

	; copy to RAM
	ldr	r0, =|Image$$RO$$Base|
	mov r1, #0
	; RO
	ldr r3, =|Image$$RO$$Limit|
	subs r2, r3, r0
	; RW
	ldr r3, =|Image$$RW$$Base|
	ldr r4, =|Image$$RW$$Limit|
	subs r3, r4, r3
	add r2, r2, r3
	; INIT
	ldr r3, =|Image$$INIT$$Base|
	ldr r4, =|Image$$INIT$$Limit|
	subs r3, r4, r3
	add r2, r2, r3	
    
    ; sector aligned
    mov  r2, r2, LSR #9
    mov  r3, #0x200
    add  r2, r3, r2, LSL #9
	
	bl	NF_Read

	tst	r0, #0x0
	beq	ok_nand_read
	
ok_nand_read

	; move back
	ldr r1, =|Image$$RO$$Base|
	ldr r2, =|Image$$INIT$$Limit|
	ldr r3, =|Image$$RO$$Limit|
	; RW
	ldr r4, =|Image$$RW$$Base|
	ldr r5, =|Image$$RW$$Limit|
	subs r4, r5, r4
	add r3, r3, r4	
	add r2, r1, r2
1
	cmp	r1, r3
	ldrcc	r4, [r2], #4       
	strcc	r4, [r1], #4
	bcc	%B1	

	; verify
;	mov	r0, #0
;	ldr	r1, =|Image$$RO$$Base|
;	mov	r2, #0x400	; 4 bytes * 1024 = 4K-bytes
;go_next
;	ldr	r3, [r0], #4
;	ldr	r4, [r1], #4
;	teq	r3, r4
;	bne	notmatch
;	subs	r2, r2, #4
;	beq	done_nand_read	
;	bne	go_next
;notmatch
;1	b	%B1
done_nand_read

	mov	pc, r10  
	

wait_idle PROC
        MOV      r1,#0x4e000000
        B        |L1.476|
|L1.460|
        MOV      r0,#0
|L1.464|
        ADD      r0,r0,#1
        CMP      r0,#0xa
        BLT      |L1.464|
|L1.476|
        LDRB     r0,[r1,#0x10]
        TST      r0,#1
        BEQ      |L1.460|
        MOV      pc,lr
        ENDP

NF_Read PROC
        MOV      r3,r0
        MOV      r0,r2
        ORR      r2,r1,r2
        STMFD    sp!,{r4-r7,lr}
        MOV      r2,r2,LSL #23
        MOVS     r2,r2,LSR #23
        MVNNE    r0,#0
        LDMNEFD  sp!,{r4-r7,pc}
        MOV      r2,#0x4e000000
        LDR      r12,[r2,#0]
        BIC      r12,r12,#0x800
        STR      r12,[r2,#0]
        MOV      r2,#0
|L1.544|
        ADD      r2,r2,#1
        CMP      r2,#0xa
        BLT      |L1.544|
        MOV      r4,r1
        MOV      r6,#0xff
        MOV      r7,#0
        MOV      r2,#0x4e000000
        ADD      r5,r1,r0
        B        |L1.652|
|L1.580|
        STRB     r7,[r2,#4]
        STRB     r4,[r2,#8]
        MOV      r0,r4,LSL #15
        MOV      r0,r0,LSR #24
        STRB     r0,[r2,#8]
        MOV      r0,r4,LSL #7
        MOV      r0,r0,LSR #24
        STRB     r0,[r2,#8]
        AND      r0,r6,r4,ASR #25
        STRB     r0,[r2,#8]
        BL       wait_idle
        MOV      r0,#0
|L1.628|
        LDRB     r1,[r2,#0xc]
        ADD      r0,r0,#1
        CMP      r0,#0x200
        STRB     r1,[r3],#1
        ADD      r4,r4,#1
        BLT      |L1.628|
|L1.652|
        CMP      r5,r4
        BHI      |L1.580|
        MOV      r0,#0x4e000000
        LDR      r1,[r0,#0]
        ORR      r1,r1,#0x800
        STR      r1,[r0,#0]
        MOV      r0,#0
        LDMFD    sp!,{r4-r7,pc}
|L1.684|
        DCD      0x0000f830
        ENDP	


SMRDATA DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz. 

        DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
    	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
    	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1 
    	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
    	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
    	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
    	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
    	DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
    	DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
    	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    



	DCD 0x32            ;SCLK power saving mode, BANKSIZE 128M/128M

    	DCD 0x30            ;MRSR6 CL=3clk
    	DCD 0x30            ;MRSR7
;    	DCD 0x20            ;MRSR6 CL=2clk
;    	DCD 0x20            ;MRSR7

    	ALIGN


    	AREA RamData, DATA, READWRITE

        ^   _ISR_STARTADDRESS
HandleReset 	#   4 
HandleUndef 	#   4
HandleSWI   	#   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ   	#   4
HandleFIQ   	#   4

;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0   	#   4
HandleEINT1   	#   4
HandleEINT2   	#   4
HandleEINT3   	#   4
HandleEINT4_7	#   4
HandleEINT8_23	#   4
HandleRSV6	#   4
HandleBATFLT   	#   4
HandleTICK   	#   4
HandleWDT	#   4
HandleTIMER0 	#   4
HandleTIMER1 	#   4
HandleTIMER2 	#   4
HandleTIMER3 	#   4
HandleTIMER4 	#   4
HandleUART2  	#   4
HandleLCD 	#   4
HandleDMA0	#   4
HandleDMA1	#   4
HandleDMA2	#   4
HandleDMA3	#   4
HandleMMC	#   4
HandleSPI0	#   4
HandleUART1	#   4
HandleRSV24	#   4
HandleUSBD	#   4
HandleUSBH	#   4
HandleIIC   	#   4
HandleUART0 	#   4
HandleSPI1 	#   4
HandleRTC 	#   4
HandleADC 	#   4

        END