📄 fx2regs.h
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EXTERN xdata volatile BYTE FLOWSTATE _AT_ 0xE6C6; //Defines GPIF flow state
EXTERN xdata volatile BYTE FLOWLOGIC _AT_ 0xE6C7; //Defines flow/hold decision criteria
EXTERN xdata volatile BYTE FLOWEQ0CTL _AT_ 0xE6C8; //CTL states during active flow state
EXTERN xdata volatile BYTE FLOWEQ1CTL _AT_ 0xE6C9; //CTL states during hold flow state
EXTERN xdata volatile BYTE FLOWHOLDOFF _AT_ 0xE6CA;
EXTERN xdata volatile BYTE FLOWSTB _AT_ 0xE6CB; //CTL/RDY Signal to use as master data strobe
EXTERN xdata volatile BYTE FLOWSTBEDGE _AT_ 0xE6CC; //Defines active master strobe edge
EXTERN xdata volatile BYTE FLOWSTBHPERIOD _AT_ 0xE6CD; //Half Period of output master strobe
EXTERN xdata volatile BYTE GPIFHOLDAMOUNT _AT_ 0xE60C; //Data delay shift
EXTERN xdata volatile BYTE UDMACRCH _AT_ 0xE67D; //CRC Upper byte
EXTERN xdata volatile BYTE UDMACRCL _AT_ 0xE67E; //CRC Lower byte
EXTERN xdata volatile BYTE UDMACRCQUAL _AT_ 0xE67F; //UDMA In only, host terminated use only
// Debug/Test
// The following registers are for Cypress's internal testing purposes only.
// These registers are not documented in the datasheet or the Technical Reference
// Manual as they were not designed for end user application usage
EXTERN xdata volatile BYTE DBUG _AT_ 0xE6F8; // Debug
EXTERN xdata volatile BYTE TESTCFG _AT_ 0xE6F9; // Test configuration
EXTERN xdata volatile BYTE USBTEST _AT_ 0xE6FA; // USB Test Modes
EXTERN xdata volatile BYTE CT1 _AT_ 0xE6FB; // Chirp Test--Override
EXTERN xdata volatile BYTE CT2 _AT_ 0xE6FC; // Chirp Test--FSM
EXTERN xdata volatile BYTE CT3 _AT_ 0xE6FD; // Chirp Test--Control Signals
EXTERN xdata volatile BYTE CT4 _AT_ 0xE6FE; // Chirp Test--Inputs
// Endpoint Buffers
EXTERN xdata volatile BYTE EP0BUF[64] _AT_ 0xE740; // EP0 IN-OUT buffer
EXTERN xdata volatile BYTE EP1OUTBUF[64] _AT_ 0xE780; // EP1-OUT buffer
EXTERN xdata volatile BYTE EP1INBUF[64] _AT_ 0xE7C0; // EP1-IN buffer
EXTERN xdata volatile BYTE EP2FIFOBUF[1024] _AT_ 0xF000; // 512/1024-byte EP2 buffer (IN or OUT)
EXTERN xdata volatile BYTE EP4FIFOBUF[1024] _AT_ 0xF400; // 512 byte EP4 buffer (IN or OUT)
EXTERN xdata volatile BYTE EP6FIFOBUF[1024] _AT_ 0xF800; // 512/1024-byte EP6 buffer (IN or OUT)
EXTERN xdata volatile BYTE EP8FIFOBUF[1024] _AT_ 0xFC00; // 512 byte EP8 buffer (IN or OUT)
// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
EXTERN xdata volatile BYTE ECCCFG _AT_ 0xE628; // ECC Configuration
EXTERN xdata volatile BYTE ECCRESET _AT_ 0xE629; // ECC Reset
EXTERN xdata volatile BYTE ECC1B0 _AT_ 0xE62A; // ECC1 Byte 0
EXTERN xdata volatile BYTE ECC1B1 _AT_ 0xE62B; // ECC1 Byte 1
EXTERN xdata volatile BYTE ECC1B2 _AT_ 0xE62C; // ECC1 Byte 2
EXTERN xdata volatile BYTE ECC2B0 _AT_ 0xE62D; // ECC2 Byte 0
EXTERN xdata volatile BYTE ECC2B1 _AT_ 0xE62E; // ECC2 Byte 1
EXTERN xdata volatile BYTE ECC2B2 _AT_ 0xE62F; // ECC2 Byte 2
// Feature Registers (FX2LP/FX1 only)
EXTERN xdata volatile BYTE GPCR2 _AT_ 0xE50D; // Chip Features
#undef EXTERN
#undef _AT_
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
sfr IOA = 0x80;
/* IOA */
sbit PA0 = 0x80 + 0;
sbit PA1 = 0x80 + 1;
sbit PA2 = 0x80 + 2;
sbit PA3 = 0x80 + 3;
sbit PA4 = 0x80 + 4;
sbit PA5 = 0x80 + 5;
sbit PA6 = 0x80 + 6;
sbit PA7 = 0x80 + 7;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr DPL1 = 0x84;
sfr DPH1 = 0x85;
sfr DPS = 0x86;
/* DPS */
// sbit SEL = 0x86+0;
sfr PCON = 0x87;
/* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
sfr TCON = 0x88;
/* TCON */
sbit IT0 = 0x88+0;
sbit IE0 = 0x88+1;
sbit IT1 = 0x88+2;
sbit IE1 = 0x88+3;
sbit TR0 = 0x88+4;
sbit TF0 = 0x88+5;
sbit TR1 = 0x88+6;
sbit TF1 = 0x88+7;
sfr TMOD = 0x89;
/* TMOD */
//sbit M00 = 0x89+0;
//sbit M10 = 0x89+1;
//sbit CT0 = 0x89+2;
//sbit GATE0 = 0x89+3;
//sbit M01 = 0x89+4;
//sbit M11 = 0x89+5;
//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr CKCON = 0x8E;
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
sfr SPC_FNC = 0x8F; // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
sfr IOB = 0x90;
/* IOB */
sbit PB0 = 0x90 + 0;
sbit PB1 = 0x90 + 1;
sbit PB2 = 0x90 + 2;
sbit PB3 = 0x90 + 3;
sbit PB4 = 0x90 + 4;
sbit PB5 = 0x90 + 5;
sbit PB6 = 0x90 + 6;
sbit PB7 = 0x90 + 7;
sfr EXIF = 0x91; // EXIF Bit Values differ from Reg320
/* EXIF */
//sbit USBINT = 0x91+4;
//sbit I2CINT = 0x91+5;
//sbit IE4 = 0x91+6;
//sbit IE5 = 0x91+7;
sfr MPAGE = 0x92;
sfr SCON0 = 0x98;
/* SCON0 */
sbit RI = 0x98+0;
sbit TI = 0x98+1;
sbit RB8 = 0x98+2;
sbit TB8 = 0x98+3;
sbit REN = 0x98+4;
sbit SM2 = 0x98+5;
sbit SM1 = 0x98+6;
sbit SM0 = 0x98+7;
sfr SBUF0 = 0x99;
#define AUTOPTR1H AUTOPTRH1 // for backwards compatibility with examples
#define AUTOPTR1L AUTOPTRL1 // for backwards compatibility with examples
#define APTR1H AUTOPTRH1 // for backwards compatibility with examples
#define APTR1L AUTOPTRL1 // for backwards compatibility with examples
// this is how they are defined in the TRM
sfr AUTOPTRH1 = 0x9A;
sfr AUTOPTRL1 = 0x9B;
sfr AUTOPTRH2 = 0x9D;
sfr AUTOPTRL2 = 0x9E;
sfr IOC = 0xA0;
/* IOC */
sbit PC0 = 0xA0 + 0;
sbit PC1 = 0xA0 + 1;
sbit PC2 = 0xA0 + 2;
sbit PC3 = 0xA0 + 3;
sbit PC4 = 0xA0 + 4;
sbit PC5 = 0xA0 + 5;
sbit PC6 = 0xA0 + 6;
sbit PC7 = 0xA0 + 7;
sfr INT2CLR = 0xA1;
sfr INT4CLR = 0xA2;
sfr IE = 0xA8;
/* IE */
sbit EX0 = 0xA8+0;
sbit ET0 = 0xA8+1;
sbit EX1 = 0xA8+2;
sbit ET1 = 0xA8+3;
sbit ES0 = 0xA8+4;
sbit ET2 = 0xA8+5;
sbit ES1 = 0xA8+6;
sbit EA = 0xA8+7;
sfr EP2468STAT = 0xAA;
/* EP2468STAT */
//sbit EP2E = 0xAA+0;
//sbit EP2F = 0xAA+1;
//sbit EP4E = 0xAA+2;
//sbit EP4F = 0xAA+3;
//sbit EP6E = 0xAA+4;
//sbit EP6F = 0xAA+5;
//sbit EP8E = 0xAA+6;
//sbit EP8F = 0xAA+7;
sfr EP24FIFOFLGS = 0xAB;
sfr EP68FIFOFLGS = 0xAC;
sfr AUTOPTRSETUP = 0xAF;
/* AUTOPTRSETUP */
// sbit EXTACC = 0xAF+0;
// sbit APTR1FZ = 0xAF+1;
// sbit APTR2FZ = 0xAF+2;
sfr IOD = 0xB0;
/* IOD */
sbit PD0 = 0xB0 + 0;
sbit PD1 = 0xB0 + 1;
sbit PD2 = 0xB0 + 2;
sbit PD3 = 0xB0 + 3;
sbit PD4 = 0xB0 + 4;
sbit PD5 = 0xB0 + 5;
sbit PD6 = 0xB0 + 6;
sbit PD7 = 0xB0 + 7;
sfr IOE = 0xB1;
sfr OEA = 0xB2;
sfr OEB = 0xB3;
sfr OEC = 0xB4;
sfr OED = 0xB5;
sfr OEE = 0xB6;
sfr IP = 0xB8;
/* IP */
sbit PX0 = 0xB8+0;
sbit PT0 = 0xB8+1;
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