📄 tb.rpt
字号:
| | | | | | +------------- LC11 |4count:50|QD
| | | | | | | +----------- LC3 |4count:50|QC
| | | | | | | | +--------- LC13 |4count:50|QB
| | | | | | | | | +------- LC14 |4count:50|QA
| | | | | | | | | | +----- LC15 :25
| | | | | | | | | | | +--- LC2 :63
| | | | | | | | | | | | +- LC5 :80
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> - * * * - - * * * * - - - | * - | <-- |4count:44|QC
LC8 -> - * * * * - - - - - - - - | * - | <-- |4count:44|QB
LC9 -> - * * * * * - - - - - - - | * - | <-- |4count:44|QA
LC11 -> - - * - - - * * * * - - - | * - | <-- |4count:50|QD
LC3 -> - - - - - - * * - - - * - | * - | <-- |4count:50|QC
LC13 -> - - - - - - * * * - - * - | * - | <-- |4count:50|QB
LC14 -> - - - - - - * * * * - * - | * - | <-- |4count:50|QA
Pin
3 -> * - - - - - - - - - - - - | * - | <-- a
10 -> - - - - - - - - - - * - - | * - | <-- datarx
44 -> - - - * * * - - - - - - - | * - | <-- load
37 -> - - - - - - - - - - - - - | - - | <-- rxclk
40 -> - - - - - - - - - - - - - | - - | <-- txclk
27 -> - * * - - - - - - - - - - | * - | <-- txen
LC22 -> - * - - - - - - - - - - * | * - | <-- :66
LC24 -> - - * - - - - - - - - - - | * - | <-- :81
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\work\tbe\tb.rpt
tb
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC21 int1
| +--------------------- LC29 :26
| | +------------------- LC20 :27
| | | +----------------- LC23 :28
| | | | +--------------- LC27 :29
| | | | | +------------- LC26 :30
| | | | | | +----------- LC25 :32
| | | | | | | +--------- LC17 :34
| | | | | | | | +------- LC18 :64
| | | | | | | | | +----- LC19 :65
| | | | | | | | | | +--- LC22 :66
| | | | | | | | | | | +- LC24 :81
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC29 -> * - * - - - - - - - - - | - * | <-- :26
LC20 -> * - - * - - - - - - - - | - * | <-- :27
LC23 -> * - - - * - - - - - - - | - * | <-- :28
LC27 -> * - - - - * - - - - - - | - * | <-- :29
LC26 -> * - - - - - * - - - - - | - * | <-- :30
LC25 -> * - - - - - - * - - - - | - * | <-- :32
LC17 -> * - - - - - - - - - - - | - * | <-- :34
LC18 -> - - - - - - - - - * - - | - * | <-- :64
LC19 -> - - - - - - - - - - * - | - * | <-- :65
Pin
37 -> - - - - - - - - - - - - | - - | <-- rxclk
40 -> - - - - - - - - - - - - | - - | <-- txclk
LC15 -> * * - - - - - - - - - - | - * | <-- :25
LC2 -> - - - - - - - - * - - - | - * | <-- :63
LC5 -> - - - - - - - - - - - * | - * | <-- :80
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\work\tbe\tb.rpt
tb
** EQUATIONS **
a : INPUT;
b : INPUT;
datarx : INPUT;
load : INPUT;
rxclk : INPUT;
txclk : INPUT;
txen : INPUT;
-- Node name is 'c'
-- Equation name is 'c', location is LC012, type is output.
c = LCELL(!a $ GND);
-- Node name is 'datatx'
-- Equation name is 'datatx', location is LC007, type is output.
datatx = LCELL( _EQ001 $ _LC009);
_EQ001 = _LC001 & _LC009 & _LC022 & !txen
# _LC008 & !_LC009 & _LC022
# !_LC009 & txen;
-- Node name is 'int0'
-- Equation name is 'int0', location is LC016, type is output.
int0 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC001 & !_LC008 & !_LC009 & _LC011 & _LC024 & !txen;
-- Node name is 'int1'
-- Equation name is 'int1', location is LC021, type is output.
int1 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC015 & !_LC017 & !_LC020 & !_LC023 & _LC025 & _LC026 &
_LC027 & _LC029;
-- Node name is '|4count:44|:46' = '|4count:44|QA'
-- Equation name is '_LC009', type is buried
_LC009 = DFFE( _EQ004 $ load, GLOBAL(!txclk), VCC, VCC, VCC);
_EQ004 = _LC009 & load;
-- Node name is '|4count:44|:45' = '|4count:44|QB'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _EQ005 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
_EQ005 = _LC008 & !_LC009 & load
# !_LC008 & _LC009 & load;
-- Node name is '|4count:44|:44' = '|4count:44|QC'
-- Equation name is '_LC001', type is buried
_LC001 = DFFE( _EQ006 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
_EQ006 = !_LC001 & _LC008 & _LC009 & load
# _LC001 & !_LC008 & load
# _LC001 & !_LC009 & load;
-- Node name is '|4count:50|:46' = '|4count:50|QA'
-- Equation name is '_LC014', type is buried
_LC014 = DFFE( _EQ007 $ !_LC011, _LC001, VCC, VCC, VCC);
_EQ007 = !_LC011 & _LC014;
-- Node name is '|4count:50|:45' = '|4count:50|QB'
-- Equation name is '_LC013', type is buried
_LC013 = DFFE( _EQ008 $ GND, _LC001, VCC, VCC, VCC);
_EQ008 = !_LC011 & _LC013 & !_LC014
# !_LC011 & !_LC013 & _LC014;
-- Node name is '|4count:50|:44' = '|4count:50|QC'
-- Equation name is '_LC003', type is buried
_LC003 = DFFE( _EQ009 $ GND, _LC001, VCC, VCC, VCC);
_EQ009 = !_LC003 & !_LC011 & _LC013 & _LC014
# _LC003 & !_LC011 & !_LC013
# _LC003 & !_LC011 & !_LC014;
-- Node name is '|4count:50|:43' = '|4count:50|QD'
-- Equation name is '_LC011', type is buried
_LC011 = DFFE( _EQ010 $ GND, _LC001, VCC, VCC, VCC);
_EQ010 = _LC003 & !_LC011 & _LC013 & _LC014;
-- Node name is ':25'
-- Equation name is '_LC015', type is buried
_LC015 = DFFE( datarx $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':26'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _LC015 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _LC029 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':28'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _LC020 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':29'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( _LC023 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _LC027 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':32'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _LC026 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC017', type is buried
_LC017 = DFFE( _LC025 $ GND, GLOBAL( rxclk), VCC, VCC, VCC);
-- Node name is ':63'
-- Equation name is '_LC002', type is buried
_LC002 = DFFE( _EQ011 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
_EQ011 = _LC003 & _LC013 & _LC014;
-- Node name is ':64'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _LC002 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
-- Node name is ':65'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE( _LC018 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
-- Node name is ':66'
-- Equation name is '_LC022', type is buried
_LC022 = DFFE( _LC019 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
-- Node name is ':80'
-- Equation name is '_LC005', type is buried
_LC005 = DFFE( _LC022 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
-- Node name is ':81'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _LC005 $ GND, GLOBAL(!txclk), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\work\tbe\tb.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000AE' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,147K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -